Samsung Electronics Co., Ltd.

Jaehyoung Choi

Cheoljin Cho

Jungmin Park

Jaesoon Lim

Younsoo Kim

Jinho Kim

Hansoo Kim

Yoosang Hwang

Bong-Soo Kim

Sunil Shim

Byoungkeun Son

Wonseok Cho

Jae-Joo Shim

Hanjin Lim

Sukhun Choi

Kyung-Eun Kim

Ju-Young Lim

Semyeong Jang

Yongkwan Kim

Youngsoo An

Mingu Kim

Hiroki Sato

Naoki Yamada

Younjoung Cho

Tsubasa Shiratori

HyungSuk Jung

Kyuho Cho

Sunmin Moon

Sangyeol Kang

Youngbin Lee

Jaewan Chang

Intak Jeon

Gabjin Nam

Chin Moo Cho

Chayoung Yoo

A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.

Capacitor and memory device

An integrated circuit device includes: a lower electrode disposed on a substrate; an insulating support pattern supporting the lower electrode; a dielectric film surrounding the lower electrode and the insulating support pattern; a high-k interface layer arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, wherein the high-k interface layer contacts the insulating support pattern and includes a zirconium oxide layer; and an upper electrode disposed adjacent the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.

Integrated circuit device

Provided is a method of fabricating a capacitor. The method of fabricating a capacitor may include forming a first electrode, forming a dielectric layer on the first electrode, forming a second electrode on the dielectric layer, and applying, between the first electrode and the second electrode, a voltage outside an operating voltage range applied during operation or a current outside an operating current range applied during operation.

Methods of fabricating capacitor and semiconductor device including the capacitor

A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode including an outer protective layer, a conductive layer between opposing sidewalls of the outer protective layer, and an inner protective layer between opposing sidewalls of the conductive layer, a first supporter pattern on a side surface of the lower electrode, the first supporter pattern including a supporter hole, a dielectric layer on a surface of each of the lower electrode and the first supporter pattern, and an upper electrode on the dielectric layer. The outer protective layer includes titanium oxide, the conductive layer includes titanium nitride, and the inner protective layer includes titanium silicon nitride. In a horizontal cross-sectional view, the outer protective layer has an arc shape that extends between the dielectric layer and the conductive layer.

Semiconductor devices including lower electrodes including inner protective layer and outer protective layer

Capacitor and DRAM device including the same

A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.

Semiconductor device having supporters and method of manufacturing the same

A semiconductor device comprises a capacitor that includes a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode. The dielectric layer comprises a first high-k dielectric layer between the first electrode and the second electrode, a first silicon oxide layer between the first high-k dielectric layer and the second electrode, and a first aluminum oxide layer between the first high-k dielectric layer and the second electrode.

Semiconductor device including capacitor

A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.

Semiconductor devices having air spacers and methods of manufacturing the same

A trialkylsilane-based silicon precursor compound may be expressed by Si(R)X, i=1-3, where each of 'R', 'R', and &#x201c;R&#x201d; is a hydrogen or an alkyl having 1-5 carbon(s), all of &#x201c;R&#x201d;, &#x201c;R&#x201d;, and &#x201c;R&#x201d; are not hydrogen, &#x201c;X&#x201d; is one of hydrogen, a hydroxyl group, an amide group, an alkoxide group, a halide group, or Si(R*), and &#x201c;R*&#x201d; is a hydrogen or an alkyl group having 1&#x2dc;5 carbon(s).

Method of forming a layer using a trialkylsilane silicon precursor compound

A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Semiconductor memory device comprising three-dimensional memory cell array

A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

A semiconductor device includes a substrate and a doped hafnium oxide layer disposed on the substrate, the doped hafnium oxide layer including a hafnium oxide layer doped with doping atoms and having tetragonal unit lattices, an ion size of the doping atom being greater than an ion size of a hafnium atom.

Semiconductor devices including a dielectric layer

Growing community of inventors

Hwaseong-si, South Korea

Jaehyoung Choi