Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Jaehoon Jang

Sunil Shim

Hansoo Kim

Jaehun Jeong

Wonseok Cho

Kihyun Kim

Woonkyung Lee

Sunghoi Hur

Jae-Joo Shim

Sung-Min Hwang

Hoosung Cho

Kyoung-Hoon Kim

Byeong-In Choe

Changhyun Lee

Woojin Cho

Jaeduk Lee

Jungdal Choi

Donghyuk Chae

Youngho Lim

Su-Youn Yi

Jin-Sung Lee

Kihyun Hwang

Jang-Gn Yun

Byoungkeun Son

Kwang Soo Seol

Jaeyoung Ahn

Jinsoo Lim

Jin-Soo Lim

Juyul Lee

Doogon Kim

Chadong Yeo

Jongsik Chun

Wookhyoung Lee

Jin-Yong Oh

Jeonghyuk Choi

Jeehoon Han

Jinman Han

Joongshik Shin

Hyunmog Park

Siyoung Choi

Sungmin Hwang

Jongkeun Kim

Ju-Young Lim

Jin-Kyu Kang

Suyoun Lee

Sejun Park

Yonghwa Han

Sukjin Yun

Sung-Hwan Jang

Hyoungsub Kim

Kinam Kim

Gilsung Lee

Daewoong Kang

Sohyeon Lee

Minyeong Song

Okcheon Hong

Yongjik Park

Seungwan Hong

Dongsung Woo

Myungchul Ryu

Sunhil Shim

Chulmin Park

Sungmi Hwang

Kyungeun Park

Jongkwang Lim

An electronic device includes a display, and a hinge assembly foldable together with the display and corresponding to a folding area of the display. The hinge assembly includes a hinge bracket defining first and second hinge axes, first and second rotators connected to the hinge bracket and respectively rotatable about the first and second hinge axes, first and second sliders connected to the hinge bracket, respectively slidable relative to the hinge bracket in a direction parallel with the hinge axes, and spaced apart from each other in the direction, and an elastic member between the first and second sliders and providing an elastic force in the direction. The first and second rotators respectively include first and second helical structures having a helical shape with the first and second hinge axes as a center, and are each connected to the first and second sliders through the first and second helical structures.

Hinge assembly and electronic device including the same

Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.

Three-dimensional semiconductor memory device

A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

Semiconductor device having a peripheral active pattern and method of manufacturing the same

A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.

Three-dimensional semiconductor device

A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.

Three-dimensional semiconductor memory device and method of operating the same

Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

Semiconductor device having staggered pillars

A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells

Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Three-dimensional semiconductor memory device having sidewall and interlayer molds

Disclosed is a nonvolatile memory having a memory cell array including a plurality of cell strings, each cell string including memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the memory cells and the substrate, and a string selection transistor between the memory cells and a bit line. The memory also includes an address decoder connected to the memory cells, the string selection transistors, and the ground selection transistors, and configured to apply a ground voltage to the string selection lines, word lines, and ground selection line. Further, the memory includes a read/write circuit connected to the string selection transistors through bit lines, and at least one first memory cell maintains a threshold voltage higher than a threshold voltage distribution corresponding to an erase state.

Three-dimensional nonvolatile memory and operating method of three-dimensional nonvolatile memory

A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Non-volatile memory devices, operating methods thereof and memory systems including the same

Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors

Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

Nonvolatile memory devices having a three dimensional structure utilizing strapping of a common source region and/or a well region

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Seongnam-si, South Korea

Jaehoon Jang