Hyundai Electronics Industries Co. Ltd.

Hyundai Microelectronics Co., Ltd.

Jae Sung Roh

Sang Hyun Kim

Bong Soo Kim

Jeong Mo Hwang

Nam Hoon Cho

Methods of forming a MOS transistor having dual gates minimizes impurity channeling and diffusion that can occur during impurity injection and activating processes. A method of fabricating the transistor includes the steps of forming a first conduction type well and a second conduction type well in a semiconductor substrate having an isolation region and an active region formed therein. Then, a gate oxide film is formed on an entire surface of the substrate, and a polysilicon layer is deposited on the gate oxide film preferably at a temperature of about 660&deg; C. to about 700&deg; C. and a pressure of about 10 to about 300 Torr. Next, portions of the polysilicon layer and the gate oxide film are selectively removed to form a gate electrode on each of the wells. Impurity ions are injected, having a conduction type opposite a conduction type of the corresponding well, into an exposed surface of each of the wells, to form lightly doped impurity regions. Insulating film sidewalls are formed at sides of each of the gates. Then, first conduction type impurity ions are heavily injected into a surface of the exposed first conduction type well and into the gate electrode formed on the first conduction type well. Also, second conduction type impurity ions are heavily injected into a surface of the exposed second conduction type well and into the gate electrode formed on the second conduction type well. Next, a first heat treatment is conducted in an oxygen ambient and a second heat treatment is conducted in a nitrogen ambient, to diffuse the impurities.

Method for fabricating MOS transistor having dual gate

A method for fabricating a contact pad for a semiconductor device, including the steps of forming device isolation layers in a semiconductor substrate to define active regions, forming a plurality of wordlines crossing the active regions, forming an insulating layer on an entire surface, and selectively removing the insulating layer on storage node contact regions, a bitline contact region, and the device isolation layer in contact with the bitline contact region, so as to form an epitaxial growth blocking layer, and conducting an epitaxial growth using the epitaxial growth blocking layer as a mask, to form a storage node contact pad as well as a bitline contact pad by causing an epitaxial layer grown in the bitline contact region to extend laterally toward the device isolation layer.

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Kyonggi-do, South Korea

Jae Sung Roh