Dongbu Electronics, Co. Ltd.

Jae-Suk Lee

Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer formed on the barrier metal layer, and a copper line layer made of a Cu&#x2014;Ag&#x2014;Au solid solution. A disclosed example method of manufacturing a semiconductor device reduces and/or prevents contact characteristic degradation of the barrier metal layer with the silicon substrate or the damascene insulating layer. In addition, by forming the copper line layer made of the Cu&#x2014;Ag&#x2014;Au solid solution, long term device reliability may be improved.

Semiconductor devices and methods for manufacturing the same

Semiconductor devices and methods of manufacturing the same are disclosed. In a disclosed method, a dangling bond in the active region(s) is removed by providing an enough Hin the PMD liner layer and the interlayer insulating layer directly contacting the active regions, and then gradually diffusing the Hin a subsequent heat treatment. The method includes forming a gate electrode having a side wall spacer, forming source and drain regions, forming a PMD liner layer by sequentially forming a SiO:H layer, a SiON:H layer and a SiN:H layer above the gate electrode and the source and drain regions, forming an interlayer insulating layer above the PMD liner layer, and diffusing hydrogen in the PMD liner layer and the interlayer insulating layer to the source and drain region by Nannealing or Ar annealing.

Semiconductor devices and methods of manufacturing the same

Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being destroyed due to electro-migration (EM) and stress-migration (SM). An illustrated metal interconnection line includes: a semiconductor substrate; a metal pattern on the substrate; a glue pattern under the metal pattern; an anti-reflection pattern on the metal pattern; and dummy patterns surrounding side walls of the metal pattern.

Metal interconnection lines of semiconductor devices and methods of forming the same

A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality of group IIIA element atom layers into the plurality of silicon atom layers. The plurality of group IIIA element atom layers may comprise Al, Ga, In, and/or Tl.

Methods for forming a P-type polysilicon layer in a semiconductor device

A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes forming a photoresist pattern for ion implantation, implanting ions into the aluminum layer, and annealing by using a rapid thermal process.

Method for forming an aluminum contact

Semiconductor devices and methods of fabricating the same are disclosed. A disclosed method comprises: partially forming a first gate stack; partially forming a second gate stack adjacent the first gate stack; forming a first interlayer dielectric; and completing the formation of the first and second gate stacks after the first interlayer dielectric has filled a distance between the first and second gate electrodes.

Semiconductor devices and methods of fabricating the same

High quality dielectric layers may be achieved without introducing excessive impurities when a semiconductor device is manufactured by a method that includes forming a lower wire layer on a structure above a semiconductor substrate, forming a silicon rich oxide layer having a refractive index of 0.45-1.55 on the lower wire layer and the structure, implanting carbon and oxygen (e.g., CO) into the silicon rich oxide (SRO) layer, and forming an organosilicate glass layer by heat-treating the implanted SRO layer.

Method for manufacturing semiconductor device

The present invention relates to a semiconductor device fabrication method, which includes forming an inter metal dielectric on a semiconductor substrate having wirings and planarizing the inter metal dielectric through a chemical mechanical polishing, wherein the inter metal dielectric is formed by carrying out at least one cycle of depositing polycrystalline silicon, plasma-processing the polycrystalline silicon, and oxidizing the polycrystalline silicon.

Method for fabricating semiconductor device

A semiconductor device includes a semiconductor substrate and metal wiring formed by alternately depositing aluminum layers and copper layers on the semiconductor substrate so that a top layer of the metal wiring is an aluminum layer. The metal wiring is fabricated by alternately depositing an aluminum layer and a copper layer on a semiconductor substrate a predetermined number of times to form a metal wiring layer having an aluminum top layer. A photoresist film pattern is formed on the metal wiring layer and metal wiring is formed by performing an etching process on the metal wiring layer using the photoresist film pattern as a mask.

Growing community of inventors

Icheon, South Korea

Jae-Suk Lee