Qualcomm Incorporated

Other

Jae Sik Lee

Hong Bok We

Dong Wook Kim

Shiqun Gu

Kyu-Pyung Hwang

Young Kyu Song

Chin-Kwan Kim

Ratibor Radojcic

Jon Gregory Aday

A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

High density fan out package structure

A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

Semiconductor package on package structure and method of forming the same

A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

Substrate block for PoP package

Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.

Stacked package configurations and methods of making the same

Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a surface of the substrate inside an area defined by scribe lines of the substrate. A crack stop structure is provided for the semiconductor device that includes a polymer dielectric layer coating that fills the trenches with a polymer dielectric material and provides a dielectric layer over the surface of the substrate inside the area. The polymer dielectric layer coating and trenches are configured to reduce cracking or chipping of the substrate in the area defined by scribe lines after cutting.

Polymer crack stop seal ring structure in wafer level package

Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer.

Integrated device comprising flexible connector between integrated circuit (IC) packages

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Interposer for a package-on-package structure

Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Integrated device package comprising silicon bridge in an encapsulation layer

A semiconductor package according to some examples of the disclosure may include a substrate having a bridge embedded in the substrate, a first and second die coupled to the substrate, and a plurality of electrically conductive bridge interconnects in the substrate coupling the bridge to the first and second die. The plurality of electrically conductive bridge interconnects may have a first bridge contact layer directly coupled to the bridge, a first solder layer on the first bridge contact layer, a second bridge contact layer on the first solder layer, a second solder layer on the second bridge contact layer, and a die contact directly coupled to one of the first and second die where the plurality of electrically conductive bridge interconnects are embedded in the substrate.

Semiconductor package with high density die to die connection and method of making the same

A substrate includes a plurality of vias that are lined with dielectric polymer having a substantially uniform thickness. This substantial uniform thickness provides a lumen within each dielectric-polymer-layer-lined via that is substantially centered within the via. Subsequent deposition of metal into the lumen for each dielectric-polymer-layer-lined via thus provides conductive vias having substantially centered metal conductors.

Substrate with conductive vias

A semiconductor device may include a first semiconductor die. A passivation layer supports the first semiconductor die. The passivation layer may include a first via having a barrier layer and a first redistribution layer (RDL) conductive interconnect coupled to the first via through the barrier layer. The first via may couple the first semiconductor die to the first RDL conductive interconnect.

Damascene re-distribution layer (RDL) in fan out split die application

A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

Power distribution improvement using pseudo-ESR control of an embedded passive capacitor

Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Integrated device comprising via with side barrier layer traversing encapsulation layer

An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a surface of the substrate that faces a first semiconductor die and a second semiconductor die. The semiconductor bridge may be disposed within a cavity extending through a photo-sensitive layer on the surface of the substrate. The semiconductor bridge may have an exposed, second surface substantially flush with the photo-sensitive layer. The first semiconductor die and the second semiconductor die are supported by the substrate and coupled together through the semiconductor bridge.

Cavity bridge connection for die split architecture

Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.

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San Diego, CA, United States of America

Jae Sik Lee