Samsung Electronics Co., Ltd.

Jae-Sik Chung

Dong-Hyeon Jang

Seung-Duk Baek

Kang-Wook Lee

Gu-Sung Kim

Hyun-Soo Chung

In-Young Lee

Seung-Kwan Ryu

Young-hee Song

Myeong-Soon Park

Sung-min Sim

A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Chipstack package and manufacturing method thereof

A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only 'known-good die' before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Chip stack package and manufacturing method thereof

A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

Wafer level chip scale package having a gap and method for manufacturing the same

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Asan-si, South Korea

Jae-Sik Chung