Samsung Electronics Co., Ltd.

Skhynix Inc.

Jae-Man Yoon

Dong-Gun Park

Choong-Ho Lee

Seong-goo Kim

Bong-Soo Kim

Chul Ho Lee

Kang-yoon Lee

Hyeoung-won Seo

Seung-bae Park

Hyeoung-Won Seo

Dong-Won Kim

Hee-Soo Kang

Gyo-young Jin

Sang-Yeon Han

Won-sok Lee

Hui-Jung Kim

Eun-jung Yun

Hyun-Woo Chung

Jeong-Dong Choe

Sung-min Kim

Yong-Chul Oh

Du-Heon Song

Se-Myeong Jang

Young-Joon Ahn

Hyun-Ju Sung

Woun-suck Yang

Woun-Suck Yang

Moon-suk Yi

Tae-Yong Kim

Yeong-taek Lee

Makoto Yoshida

Chang-Woo Oh

Min-sang Kim

Sang-hyun Lee

Yun-Gi Kim

Tai-Su Park

Eun-Suk Cho

Ming Li

Hye-Jin Cho

Hyeoungwon Seo

Yun-Jae Lee

Kang-Yoon Lee

Young-Woong Son

Wook-je Kim

Youngwoong Son

Yoshida Makoto

Hyeong-Won Seo

A method for fabricating a semiconductor device includes: forming a plurality of bit line structures over a semiconductor substrate; forming a line-type opening between the bit line structures; forming a sacrificial spacer on both sidewalls of the line-type opening; forming a line-type plug filling the line-type opening over the sacrificial spacer; forming a plurality of plug isolation openings that expose the sacrificial spacer by etching a portion of the line-type plug in a direction crossing the bit line structures; forming a plurality of air gaps by removing the exposed sacrificial spacer; removing a remaining line-type plug below the plug isolation openings to form a plurality of island-type plugs; and forming a plug isolation layer inside the plug isolation openings to isolate neighboring island-type plugs from each other.

Semiconductor device with air gap and method for fabricating the same

Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4Fstructure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

Semiconductor memory device having vertical channel transistor and method for fabricating the same

Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

Methods of manufacturing vertical channel semiconductor devices

There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

Semiconductor device having vertical transistor and method of fabricating the same

Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

Semiconductor memory devices including a vertical channel transistor having a buried bit line

An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.

Access device having vertical channel and related semiconductor device and a method of fabricating the access device

A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode

In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.

Semiconductor memory device with vertical channel formed on semiconductor pillars

Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.

Semiconductor devices having a vertical channel transistor

According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

Transistor and method of forming the same

A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

Semiconductor device having a fin structure and method of manufacturing the same

A semiconductor device includes a first active pattern protruding from a substrate, a second active pattern on the first active pattern, a gate electrode enclosing a sidewall of the second active pattern, a conductive layer pattern on the first active pattern, a first impurity region in the first active pattern, and a second impurity region at a surface portion of the second active pattern. The first active pattern extending along a predetermined direction may have a first region and a second region. The second active pattern may have a pillar structure and the conductive layer pattern may include a metal or a metal compound.

Semiconductor device having vertical transistor formed on an active pattern protruding from a substrate

Growing community of inventors

Seoul, South Korea

Jae-Man Yoon