Samsung Electronics Co., Ltd.

Jae-Jong Han

Kong-Soo Lee

Young-Wook Park

Yong-Woo Hyung

Kyoung-Seok Kim

Seung-Mok Shin

Sang-Jin Park

Hong-bae Park

Jae-Hyun Yeo

Seong-Hoon Jeong

Young-sub You

Jung-Geun Jee

Yong-woo Hyung

Seung Mok Shin

Ho-Min Son

Byung-Ho Ahn

Taek-Jin Lim

Yoon-Goo Kang

Hwa-Sik Kim

Sun-Young Lee

Ki-Hyun Hwang

Dong-Hun Lee

Eun-jung Yun

Young-wook Park

Bon-Young Koo

Han-jin Lim

Joo-hyung Lee

Woo-Sung Lee

Sung-eui Kim

Ki-Chul Kim

Jae-young Park

Won-Seok Yoo

Ho-Kyun An

Ji-Sang Yahng

Han-ki Lee

Sung-Eui Kim

Beung-Keun Lee

Gi-Hyun Hwang

Byung-Kee Kim

Doo-Hyun Hwang

Jum-Soo Chang

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.

Semiconductor device and method of fabricating the same

A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.

Semiconductor devices having blocking layers and methods of forming the same

Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

Semiconductor devices having a vertical diode and methods of manufacturing the same

A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Method of forming nonvolatile memory device having floating gate and related device

A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

Method of forming a vertical diode and method of manufacturing a semiconductor device using the same

A layer is formed on a semiconductor wafer in an apparatus having a processing chamber, a transferring chamber, and a wafer boat. The boat having the semiconductor wafer thereon is rotated in the transferring chamber. While the boat is rotated, the boat is transferred between the transferring chamber and the processing chamber and a reaction gas is provided to the processing chamber to form the layer on the wafer.

Method of forming a layer on a wafer

Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically adsorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically adsorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically adsorb the second reactant onto the substrate.

Methods and apparatus for forming thin films for semiconductor devices

Provided is a method for manufacturing semiconductor devices including channel trenches that are separated by isolation structures. According to the process, the substrate is etched to form isolation trenches after which a sidewall oxide layer, a liner nitride layer and a field oxide layer are subsequently formed on the substrate and in the isolation trenches. The substrate is then planarized to remove upper portions of the sidewall oxide layer, the liner nitride layer and the field oxide layer to expose surface portions of the substrate between adjacent isolation trench structures. Channel trenches are then formed in the exposed surface portions of the substrate leaving residual substrate regions adjacent the isolation trench structures. These residual substrate regions are then oxidized and removed to form improved second channel trenches for the formation of transistor regions.

Method for manufacturing a semiconductor device

A first gate oxide layer pattern having a first thickness is formed in a first region of a substrate and a second gate oxide layer having a second thickness is formed in a second region of a substrate. A surface of the second gate oxide layer is selectively nitrified to form an oxynitride layer, thereby reducing a depletion effect of a poly gate and a fluctuation of threshold voltage.

Method of forming a gate oxide layer in a semiconductor device and method of forming a gate electrode having the same

In a method for forming a gate electrode having an excellent sidewall profile, after a gate structure is formed on a substrate, a first oxide film is formed on a sidewall of the gate structure and on the substrate by re-oxidizing the gate structure and the substrate under an atmosphere including an oxygen gas and an inert gas. The gate structure has a gate oxide film pattern, a polysilicon film pattern and a metal silicide film pattern. A portion of the first oxide film formed on a sidewall of the polysilicon film pattern has a thickness substantially identical to that of a portion of the first oxide film formed on a sidewall of the metal silicide film pattern. A failure of a semiconductor device having the gate electrode can be minimized because the gate electrode has an improved sidewall profile.

Method of forming a gate electrode, method of manufacturing a semiconductor device having the gate electrode, and method of oxidizing a substrate

A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.

Plasma enhanced chemical vapor deposition apparatus and method for forming nitride layer using the same

A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.

Method of manufacturing a semiconductor device including alignment mark

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Seoul, South Korea

Jae-Jong Han