Samsung Electronics Co., Ltd.

University of California

Jae Gon Lee

Ah Chan Kim

Jae Young Lee

Se Hun Kim

Youn Sik Choi

Jin Ook Song

Ho Yeon Jeon

Bong Il Park

Dong Keun Kim

Jung Hun Heo

Min Joung Lee

Si Young Kim

Sun Cheol Kwon

Andrew B Kahng

Kwang Ho Kim

Bub-chul Jeong

Jae Geun Yun

Taek Kyun Shin

Young Duk Kim

Suk Nam Kwon

Jinpyo Park

Jang Ho Cho

Gilles Dubost

Sang Wook Ju

Seung Chull Suh

Moo Kyung Kang

Yung Hei Lee

Soo Wan Hong

Young San Kim

Seok Hyeong Kang

Woo Kyeong Jeong

An electronic device includes; an intellectual property (IP) block, a thermal management unit (TMU) that detects a temperature associated with the IP block to generate a detected temperature, a clock management unit (CMU) that generates an operating clock and provides the operating clock to the IP block, a clock generator that controls operation of the CMU in generating the operating clock, a power management unit (PMU) that generates a supply voltage provided to the CMU, and a dynamic voltage frequency scaling (DVFS) block. The DVFS block includes; a critical path monitor (CPM) that monitors the operating clock, a frequency monitor that determines a current frequency for the operating clock, a target frequency module that determines a target frequency for the operating clock, an adder that compares the target frequency and the current frequency to generate frequency comparison results, and a decide voltage module that generates deciding results in response to the frequency comparison results, wherein the PMU adjusts a level of the supply voltage in response to the deciding results.

Electronic device and method of controlling temperature associated with a semiconductor device using dynamic voltage frequency scaling (DVFS)

A semiconductor device includes an intellectual property (IP) block, a clock management unit, a critical path monitor (CPM), and a CPM clock manager included in the clock management unit. The clock management unit is configured to receive a clock request signal, indicating whether the IP block requires a clock signal, from the IP block and perform clock gating for the IP block based on the received clock request signal. The CPM is configured to monitor the clock signal provided to the IP block to adjust at least one of a frequency of the clock signal provided to the IP block and a voltage supplied to the IP block. The CPM clock manager is configured to perform the clock gating for the CPM.

Semiconductor device

A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Semiconductor device, semiconductor system and method for operating semiconductor device

Semiconductor device including clock management unit for outputting clock and acknowledgment signals to an intelectual property block

Semiconductor device including clock management unit for outputing clock and acknowledgement signals to an intellectual property block

A semiconductor device includes a first intellectual property block (IP block) which includes a function unit and an interface unit; a first clock control circuit which controls a first clock source; a second clock control circuit which transmits a first clock request to the first clock control circuit, and controls a second clock source which receives a clock signal from the first clock source; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block; wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.

Semiconductor device including a clock source for generating a clock signal and a clock control circuit for controlling the clock source in hardware, a semiconductor system including the semiconductor device, and a method of operating the semiconductor device

A clock generation circuit having a deskew function and a semiconductor integrated circuit device including the same are provided. The clock generation circuit includes a clock gating circuit configured to gate an input clock signal based on a first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times a period of the input clock signal.

Clock generation circuit having deskew function and semiconductor integrated circuit device including same

A semiconductor device includes a first clock control circuit for controlling a first clock source; a second clock control circuit for sending a first clock request to the first clock control circuit in response to a block clock request from an intellectual property (IP) block, and controlling a second clock source, which receives a clock signal from the first clock source, to generate a stopped clock signal, which is a clock signal turned off for a predetermined amount of time; and a driver circuit for receiving a block control signal, and outputting the block control signal to the IP block while the short stopped clock signal is output to the IP block.

Semiconductor device for stopping an oscillating clock signal from being provided to an IP block, a semiconductor system having the semiconductor device, and a method of operating the semiconductor device

Clock management using full handshaking

Growing community of inventors

Yongin-si, South Korea

Jae Gon Lee