Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Jae Ean Lee

Young Gwan Ko

Jung Soo Byun

Tae Sung Jeong

Ik Jun Choi

Yong Ho Baek

Jae Hoon Choi

Ye Jeong Kim

Sang Kun Kim

Suk Ho Lee

Kwang Ok Jeong

Han Na Jin

A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.

Fan-out semiconductor package

A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.

Semiconductor package

A semiconductor package includes a supporting member that has a cavity and includes a wiring structure connecting first and second surfaces opposing each other. A connection member is on the second surface of the supporting member and includes a first redistribution layer connected to the wiring structure. A semiconductor chip is on the connection member in the cavity and has connection pads connected to the first redistribution layer. An encapsulant encapsulates the semiconductor chip disposed in the cavity and covers the first surface of the supporting member. A second redistribution layer includes wiring patterns embedded in the encapsulant and has exposed surfaces and connection vias that penetrate through the encapsulant to connect the wiring structure and the wiring patterns to each other.

A semiconductor package including an organic interposer includes: a semiconductor chip; a connection member on the semiconductor chip and including a pad layer, a redistribution layer, and an insulating layer; a bonding member between the semiconductor chip and the pad layer; a surface treatment layer on the pad layer and including at least one metal layer; and an under-bump metallurgy (UBM) layer embedded in the connection member. The UBM layer includes a UBM pad, at least one plating layer on the UBM pad, and a UBM via. The surface treatment layer is disposed only on one surface of the pad layer, the plating layer are is disposed only on one surface of the UBM pad, and at least a portion of a side surface of the plating layer is spaced apart from a side surface of the insulating layer surrounding the plating layer.

A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.

Carrier substrate and method of manufacturing semiconductor package using the same

An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.

Growing community of inventors

Suwon-si, South Korea

Jae Ean Lee