Mosel Vitelic Corporation

Jacson Liu

Jing-Xian Huang

Chih-Sheng Chang

Cheng-Tsung Ni

Hsin-Tang Peng

Hudy-Jong Wu

The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench. The method comprises: (1) choosing the shallow trenches with widths greater than a predetermined size and generating at least one dummy in each chosen shallow trench to form a plurality of new trenches with widths less than the predetermined size; (2) covering the surface of the semiconductor wafer with dielectric material to form a dielectric layer; (3) condensing the dielectric layer; (4) polishing the surface of the dielectric layer filled in all the shallow trenches to align the surface of the dielectric material with the surface of the components on the semiconductor wafer.

Shallow trench isolation method for a semiconductor wafer

Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer ( ) that is thin in some regions, such as the cell region, and thicker in other regions ( ), such as the periphery region. The method simultaneously provides a gate oxide layer with two or more thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to a specific embodiment of the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor ROM device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor ROM device.

Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities

A process for creating a dual damascene structure without needing an etch stop is disclosed. The process comprises the steps of: (a) providing a device substrate having a dielectric layer thereon; (b) forming a mask layer with a via pattern overlaying the dielectric layer; (c) forming a photoresist layer with a conductive line pattern aligned with said via pattern overlaying the mask layer; (d) etching part of the way through the dielectric layer using said mask layer as an etch mask, thereby transferring said via pattern into the upper half of the dielectric layer; (e) etching said mask layer and said dielectric layer using said photoresist layer as an etch mask, thereby transferring said conductive line pattern into the upper half of the dielectric layer to form a conductive line trench, and simultaneously transferring said via pattern in the upper half of the dielectric layer into the lower half of the dielectric layer to form a via opening; and (f) filling said conductive line trench and said via opening with a conductive material.

Dual damascene process

A process for fabricating a VLSI device comprising trench isolation regions. The trench isolation regions of a VLSI device is fabricated by a process comprising the following steps: Depositing and patterning pad layers on a substrate to form active regions separated from pad-layer-covered regions; forming side walls at each active region to cover portions of the active region other than its central portion; depositing a first oxide at the space surrounded by the side walls and the central portion of the active region; removing the side walls to form trenches at the active region; and depositing a second oxide on the substrate to fill the trenches and cover the first oxide, the second oxide and the first oxide together forming an oxide trench isolation region.

Method for fabricating VLSI devices having trench isolation regions

A method for fabricating a deep trench capacitor by using a patterned mask having a specific pattern thereon is provided. The specific pattern is formed by caving at least one side thereof in. The method for fabricating a deep trench capacitor includes the steps of providing a substrate, forming a deep trench having an opening by using the patterned mask with the above-described pattern within a predetermined rectangular area on the substrate, and utilizing the deep trench to form a deep trench capacitor.

Patterned mask and a deep trench capacitor formed thereby

A process for forming a contact structure of a semiconductor device includes the steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the gates, (b) forming a first dielectric layer on the oxide layer and the gates, (c) forming a second oxide layer on the first dielectric layer, and (d) removing a portion of the second oxide layer for forming first spacers alongside each of the gates. The process further includes steps of (e) removing a portion of the first dielectric layer and the first oxide layer to expose a portion of the substrate by using the first spacers as a mask for forming second spacers alongside each of the gates, (f) forming a second dielectric layer over the exposed portion of the substrate, the second spacers, and the gates, (g) forming a third dielectric layer over the second dielectric layer, and (h) executing a photolithographic and etching process on the third dielectric layer and the second dielectric layer to form the contact structure between the gates on the substrate.

Process for forming self-aligned contact of semiconductor device

The present invention relates to a shallow trench isolation method of a semiconductor wafer for filling dielectric material in each shallow trench between components on the surface of the semiconductor wafer to isolate the components electrically and prevent dishing when the chemical-mechanical polishing is performed on the surface of dielectric material in each shallow trench. The method comprises: (1) covering the surface of the semiconductor wafer with the dielectric material to form a first dielectric layer, filling the dielectric material in each shallow trench on the surface of the semiconductor wafer and the corresponding dish being formed above each shallow trench; (2) forming the second dielectric layer in each dish of the first dielectric layer; (3) polishing the surface of the semiconductor wafer to strip off the second dielectric layer in each dish of the first dielectric layer and cutting the surface of dielectric material in each shallow trench and on each component on the surface of the semiconductor wafer.

Shallow trench isolation method of a semiconductor wafer

A simplified method for forming a self-aligned contact hole is disclosed. The method comprises the steps of (a) providing a semiconductor substrate having a gate electrode and a diffusion region thereon; (b) forming a conformal layer of etch barrier material overlying the substrate surface including the diffusion region and the upper surface and the sidewalls of the gate electrode; (c) forming an insulating layer overlying the barrier layer; (d) etching an opening through the insulating layer self-aligned and borderless to the diffusion region by using the barrier layer as an etch stop; and (e) anisotropically etching the barrier layer underneath the opening, thereby exposing the diffusion region and simultaneously forming a spacer of the etch barrier material on the sidewall of the gate electrode.

Growing community of inventors

Hsin-Chu Hsien, Taiwan

Jacson Liu