Hewlett-packard Company

Other

Agilent Technologies, Inc.

Jacques Leibovitz

Clinton C Chao

Kenneth D Scholz

Voddarahalli K Nagesh

Maria L Cobarruviaz

Susan J Swindlehurst

Kim Hong Chen

Daniel J Miller

Robert Keith Crawford

Cheng-Cheng Chang

Peter F Dawson

Peter F Dawson, Deceased

V K Nagesh

Hubert A Vander Plas

Park-Kee Yu

John P Scalia

Hilmar W Spieth

Howard H Nakano

Bahram Afshari

By Shirley Dawson, Executor

Ya Yun Zhu

Greg M Irby

Edith P Prather

Kim K Chen

Uniform height solder bumps are created on a semiconductor wafer by exposing a dummy pattern of under bump metal for solder plating. The dummy pattern of exposed under bump metal follows the outer edge outline of a pattern of die that exists on the semiconductor wafer. The dummy pattern of under bump metal is exposed by removing a portion of a layer of photoresist that is deposited over the under bump metal. The dummy pattern of under bump metal is exposed on the wafer at the same time that under bump metal above the contact pads is exposed. Solder material is then plated onto the exposed under bump metal that exists above the contact pads and in the dummy pattern. The dummy pattern of exposed under bump metal around the outer edge of the die pattern causes current crowding to occur primarily at the dummy pattern of exposed under bump metal instead of at the contact pads that are on die at the outer edge of the die pattern. Because current crowding occurs primarily at the dummy pattern of exposed under bump metal instead of at the exposed under bump metal above the contact pads of the outer edge die, the plating current density across the die pattern is more uniform, thereby producing solder bumps having a more uniform height.

Method and structure for uniform height solder bumps on a semiconductor wafer

Method and structure for uniform height solder bumps on a semiconductor

A method of forming solder bumps on a wafer. The wafer includes at least one substrate, a plurality of solder-wettable pads and a solder wettable retention ring about the periphery of the wafer. The method of forming solder bumps includes forming a non-solder-wettable mask on the wafer which includes a plurality of apertures which align with the solder-wettable pads, and the solder wettable retention ring surrounds the mask. The mask and wafer are positioned within an aperture of a stencil so that the solder wettable retention ring aligns with a gap between the periphery edge of the mask and an inside edge of the aperture of the stencil. Solder paste is applied to the mask so that the solder paste fills the apertures of the mask and the gap. The solder paste is reflowed forming solder bumps on the pads and a solder ring on the solder wettable retention ring. The mask is removed after formation of the solder bumps.

Solder retention ring for improved solder bump formation

An integrated circuit redistribution structure. The integrated circuit redistribution structure includes a plurality of conductive pads located on an active side of an integrated circuit. The integrated circuit redistribution structure includes a redistribution layer and an under bump material structure for receiving a solder bump. The redistribution layer can include a first mechanically protective layer which adheres to the active side of the integrated circuit. The redistribution layer includes a plurality of conductive lines in which at least one of the conductive lines is connected to at least one conductive pad. Each conductive line includes an adhesion and diffusion barrier layer, an electrical conductor layer, and a first metallic protective layer. The under bump material structure is formed over at least one conductive line. The under bump material structure includes a solder wettable metal layer formed over the redistribution layer, and a second metallic protective layer for receiving the solder bump.

Redistribution layer and under bump material structure for converting

A silicon die, such as an integrated circuit, is reworkably bonded to a copper heat spreader. The silicon-copper bond exhibits high compliance under conditions of thermal stress even though there is a significant thermal coefficient of expansion difference between silicon and copper. A compliant adhesive is applied to the surface of one of the silicon die and the copper heat spreader and is cured. Thereafter, a thermoplastic adhesive is applied to bond the silicon die to the copper heat spreader. A composite bond is thereby produced, including a highly compliant layer and a thermoplastic layer. The die may be reworked by heating the thermoplastic adhesive until the bond begins to soften and the die is released.

Reworkable die attachment to heat spreader

The flip chip package described is comprised of a substrate, a ring structure attached to the substrate, a heat removal structure, and a chip thermally coupled to the heat removal structure. The package lid is comprised of a ring structure and a heat removal structure. The ring structure and heat removal structure are separated until after attachment of the ring structure to the substrate allowing the ring structure to be brazed to the substrate. Brazing the ring structure to the substrate decreases the mechanical stress to the chip. A die attach material, between the first major surface of the die and the first major surface of the heat removal structure, adheres the die to and thermally couples the die to the heat removal structure. The die attach layer is of a predetermined thickness and thus provides a determined low thermal resistance making the thermal performance of the package certain.

Low cost, high thermal performance package for flip chips with low

A flip-chip IC package (10) provides a thermally-conductive lid (20) attached to a backside of the chip (12) by a die attach layer (18) of a predetermined thickness range. A rim (22), preferably KOVAR iron-nickel alloy, is formed on the lid (20) with a depth (44) less than a sum (42) of a thickness of the chip, the interconnects (16), and a minimum final thickness (40) of the die attach layer (18) by a predetermined margin (46). An initial thickness of thermally-filled epoxy is applied to the backside of the chip and a layer of lid attach epoxy (24) is applied to the rim of the lid in a thickness sufficient to span the predetermined margin. The lid is floated on the die attach layer (18) with the rim of the lid surrounding the chip and floating on the lid attach material. The lid is clamped against the chip with a force sufficient to compress the die attach material to a predetermined thickness in a range less than the initial thickness and not less than the minimum final thickness (40). An oxide layer, such as an iron or iron-alloy oxide layer, is formed on the bottom surface of the rim. A spacer is placed on the backside of the chip within the die attach material (18), to define the minimum final thickness (40) of the die attach layer. A beveled or stepped vent hole is formed in the lid and plugged and sealed.

Reliable low thermal resistance package for high power flip clip ICs

The present invention is a double headed pin for electrically interconnecting a PGA substrate carrier to a surface mount printed circuit board. The double headed pins provide for a stronger interconnection to the conductive pads on the surface mount printed circuit board. The increase in contact and soldering wetting area makes the interconnections stronger and more durable.

Surface mounting pin grid arrays

A method for fabricating layers permits the accurate removal of surface material in a multi-layer multi-chip carrier. An intermediate layer of solid vias is deposited over a circuit layer attached to a substrate. The layer can be filled with a dielectric material. The substrate is attached to a substrate holder such that the intermediate layer is exposed, and the substrate holder is placed onto a rotating platen polisher with the intermediate layer facing the platen surface. Tooling presses the intermediate layer against the rotating polishing platen, allowing the substrate holder and substrate to rotate with three degrees of angular freedom, letting the substrate and intermediate layer self-align to the polishing platen in order to uniformly remove material from the intermediate layer surface. A second circuit layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure of circuit layers separated by uniformly thick dielectric and via layers. As an alternative method, substrate attached to a substrate holder is placed against the platen surface of a shaking polisher, allowing the substrate and substrate holder to self-align to the polishing platen. In a third embodiment, where metal irregularities exist along the intermediate layer surface, wiping the surface evenly with cloth soaked in an appropriate etchant can uniformly remove the unwanted metal irregularities.

Multi-layer fabrication in integrated circuit systems

An integrated circuit is reworkably attached to a circuit board in a manner that forms a compliant bond which is stable under conditions of high thermal stress and thermal coefficient of expansion mismatch. A thermoplastic adhesive having a melting temperature higher than integrated circuit operating temperature is coated on the integrated circuit and dried. The adhesive is then cured. The coated integrated circuit is bonded to the circuit board with a thermosetting epoxy having a low curing temperature, such that curing the adhesive does not damage the circuit board. The integrated circuit is readily removed from the circuit board without damaging the board by heating the integrated circuit to soften the bond between the integrated circuit and the circuit board at the thermoplastic adhesive interface. An alternate embodiment of the invention provides a copper plate interface that is soldered to the circuit board, and to which an integrated circuit is permanently bonded. Reworkability is achieved by flowing the solder bond and removing the copper plate/integrated circuit assembly.

Reworkable die attachment

A specialized etching method for producing fine-geometry gold circuit structures. Production thereof is accomplished by maintaining a constant gold etching rate. Metal etching normally slows as the amount of dissolved gold (a reaction product of the etching process) increases. To remove the dissolved gold, one method involves cooling the etchant to precipitate a gold complex therefrom. The remaining, recovered etchant is then heated and made available for continued etching. Another method involves a cathode/anode assembly which is immersed in the etchant. Activation of the assembly recovers metallic gold and regenerates the etchant. These methods, when used continuously or periodically in a dip or spray etching system, maintain a constant etching rate. As a result, fine-geometry circuit structures may be accurately produced while minimizing material costs (e.g. etchant use) and minimizing the production of undesirable waste products and disposal expenses associated therewith.

Controlled etching process for forming fine-geometry circuit lines on a

Method and apparatus for controlling the temperature of one or more electrical component chips positioned on a face of a substrate and for providing component-to-component electrical interconnect traces between the chips. One or a selected set of electrical interconnections, contained within the substrate and connected to a chip, is also connected to a column of high electrical and thermal conductivity material within the substrate that is in direct thermal contact with the working fluid in a heat pipe. The heat pipe is sealed and is contained in the substrate interior and is in electrical and thermal contact with the electronic components on a chip. The heat pipe working fluid receives heat from the electronic components through the thermally conducting column, changes phase through absorption of this heat, and transports the heat to heat dissipation means located elsewhere.

Heat pipe-electrical interconnect integration method for chip modules

A method for fabricating high density multi-chip carriers for integrated circuits includes the steps of forming a circuit pattern on a substrate, depositing a composite metal layer and a photoresist layer over the circuit pattern, forming apertures in the photoresist layer, forming solid metal vias in the apertures and, then, removing the photoresist layer. After removal of the first photoresist layer, a second photoresist layer is deposited over the solid vias and the circuit pattern. With the second photoresist layer in place, unprotected portions of the composite layer are etched away. Then, the second photoresist layer is stripped away. Next, a layer of photosensitive dielectric material is formed over the structure and, finally, sufficient portions of the photosensitive dielectric material are removed to expose the top surfaces of the solid vias.

Methods for forming high density multi-chip carriers

A method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.

Growing community of inventors

San Jose, CA, United States of America

Jacques Leibovitz