Sage Design Automation Ltd

Jacob Zelnik

Jozefus Godefridus Gerardus Pancratius Van Gisbergen

Daniel James Blakely

Rob Oomens

A method, a computer program product and a system of checking an integrated circuit layout for instances of a reference pattern is provided The methodcomprises the steps of: i) receivingthe integrated circuit layout, ii) receivinga drawing of the reference pattern from a user, iii) deductinga basic pattern definition from the drawn reference pattern, iv) determininga set of topological relation based on the drawn reference pattern, v) forminga complex pattern description which is a combination of the deducted basic pattern definition and the set of topological relations, vi) checkingthe integrated circuit layout for patterns that match the complex pattern description to find instances of the reference pattern in the integrated circuit layout, and vii) storingfound instances of the reference pattern.

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Sunnyvale, CA, United States of America

Jacob Zelnik