International Business Machines Corporation

Jacek G Smolinski

Brian J Grenon

Richard Alan Haight

Michael Straight Hibbs

James Allan Bruce

Alfred Wagner

Timothy E Neary

Dennis A Schmidt

Dennis M Hayden

Raymond E Rochefort

J Peter Levin

Edward W Conrad

James A Culp

Kenneth T Settlemyer, Jr

Daria Rose Dooling

Ralph James Williams

David S O'Grady

Gregory J Dick

Stephen D Thomas

J Richard Behun

Denis Marc Rigaill

Donald P Perley

Ann Rand Burke

John D Nickel

Karen Marie Badger

The subject matter disclosed herein relates to determining a lithographic set point using simulations of optical proximity correction verification. In one embodiment, a computer-implemented method of determining a lithographic tool set point for a lithographic process is disclosed. The method may include: providing a model of a production lithographic process including simulations of printed shapes; analyzing the model of the production lithographic process to determine whether a set of structures on a production mask used in the production lithographic process to create the printed shapes will fail under a plurality of set points; determining an operating region of set points where the set of structures on the production mask does not fail; and establishing a set point location within the operating region based upon a set point selection function.

Determining lithographic set point using optical proximity correction verification simulation

The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region.

Method for creating electrically testable patterns

A method is provided for performing optical proximity correction ('OPC') verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using the photomask. A plurality of areas of the photomask, aerial image or photoresist image are identified which incorporate the identified features of concern, where the plurality of identified areas occupy substantially less area than the total area of the photomask that is occupied by features. Enhanced OPC verification limited to the plurality of identified areas is then performed to identify problems of at least one of the photomask, aerial image or photoresist image.

OPC verification using auto-windowed regions

A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data

A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.

Design verification

Fill pattern inspection system and method where the fill patterns are inspected to a different criteria than the primary pattern or not inspected at all. The fill pattern images are marked such that they may be identified by easily recognizable shapes or designations to avoid unnecessary inspections and repairs in the fill areas. Alternatively, subresolution markers are placed in an image data for locating fill pattern areas. A software tool is also programmed to automatically detect the subresolution markers during inspection and to inspect the regions on a plate which correspond to the subresolution markers in the image data at a different level of criteria than one which is employed for primary pattern inspection.

Fill pattern inspection

A method of repairing defects on masks includes the step of providing a coating on the mask to prevent damage to clear regions of the mask from laser ablation splatter, laser ablation caused quartz pitting, laser deposition staining, and FIB caused gallium staining. The coating is a metal, a polymer, or a carbon material. The coating is formed on clear regions of the mask as well as either over or under the light absorbing material of the mask. A coating comprising a thin copper layer significantly improves imaging with the ion beam while protecting clear regions of the mask from FIB stain. A coating formed of a photosensitive polymer is used to etch opaque defects. While wanted opaque regions adjacent an opaque defect are also etched in this etch step, these created clear defects are then repaired in a subsequent FIB deposition step while a copper coating protects adjacent clear regions from FIB stain. In another embodiment, opaque defects are repaired with a short pulse duration laser without damage to underlying quartz or adjacent clear regions while avoiding the need for a coating.

Methods for repair of photomasks

A method and apparatus for repairing black dot defects connected to a circuit pattern in photomasks such as a photomask having a patterned chromium film on a glass substrate comprises using an energy source in the form of an energy beam to first sever the connected black dot defect from the chrome pattern forming a space between the defect and the chrome pattern. The remaining severed black dot defect is then removed using the same or different energy beam to remove the remainder of the chrome defect. An apparatus for removing black dot defects and photomasks produced by the method and apparatus of the invention are also provided.

Cut and blast defect to avoid chrome roll over annealing

Method for repair of photomasks

A method is provided for making sublithographic structures, such as programmed defect masks. The method comprises the steps of forming a layer of base material on a substrate, the base material being selectively definable from the substrate, forming a layer of photosensitive material over the layer of material, selectively exposing a plurality of image segments in the photosensitive material in which segments are offset from each other by a sub-lithographic dimension in a first direction and a different dimension in a second direction and a sub-plurality of the segments pass over the layer of base material, and developing the photosensitive material to expose the layer within the sub-plurality of segments. Also provided is the resulting programmed defect mask with defects under 0.1 .mu.m in size.

Programmed defect mask with defects smaller than 0.1 .mu.m

Photomask repaired from black dot defect

A method and system for detecting defects in the design of a photolithographic mask or a printed wafer. It derives an adaptive inspection algorithm that allows for a tighter inspection of a mask to a data set which has repeatable differences. The inspection should allow flexibility to remove un-important differences while maintaining a tight inspection capability.

Growing community of inventors

Jericho, VT, United States of America

Jacek G Smolinski