Globalfoundries Inc.

Isabelle Ferain

Haiting Wang

Yong Meng Lee

Johannes M Van Meer

Tien-Ying Luo

Cuiqin Xu

Feng Zhou

Jean-Baptiste Laloe

Padmaja Nagaiah

One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.

Stress memorization techniques for transistor devices

An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.

Depositing an etch stop layer before a dummy cap layer to improve gate performance

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Ballston Spa, NY, United States of America

Isabelle Ferain