International Business Machines Corporation

Irving T Ho

Jacob Riseman

Hwa N Yu

Robert A Henle

A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grown on the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.

Single electrode U-MOSFET random access memory

A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grownon the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.

Method for making single electrode U-MOSFET random access memory

A method for forming a narrow, such as a submicrometer, dimensioned mask opening on a silicon body involving forming a first insulator region having substantially a horizontal surface and a substantially vertical surface. A second insulator is applied on both the horizontal surface and substantially vertical surfaces. The second insulator is composed of a material different from that of the first insulator layer. Reactive ion etching of the second layer removes the horizontal layer and provides a narrow dimensioned second insulator region on the silicon body. The surface of the silicon body is then thermally oxidized. The narrow dimensioned second insulator region is removed to form a narrow dimensioned mask opening.

Method for forming a narrow dimensioned mask opening on a silicon body

A method for forming diffusions having narrow, for example, submicrometer dimensions in a silicon body which involves forming insulator regions on a silicon body, which insulator regions have substantially horizontal surfaces and substantially vertical surfaces. A layer having a desired dopant concentration is formed thereon, both on the substantially horizontal surfaces and the substantially vertical surfaces. Reactive ion etching of the layer acts to substantially remove only the horizontal layer and provides a narrow dimensioned layer having a desired dopant concentration in the substantially vertical surfaces. Heating of the body at a suitable temperature is accomplished so as to produce the movement of the dopant into the silicon body by diffusion to form diffusions having narrow, such as submicrometer dimensions, therein.

Method for forming diffusions having narrow dimensions utilizing

Disclosed is a dynamic memory cell storing digital information, particularly adapted for integrated semiconductor circuit fabrication. The circuit configuration has a bipolar transistor with information storage preferrably in the capacitance of the junctions, and a field effect transistor (FET) for selectively injecting charge into the capacitances. In integrated form, isolation is required only between columns of cells, a buried subcollector forming a common sense line for the entire column, while each of the base regions (also used as a first controlled region of the FET) requires no external contact at all. A further impurity region formed into each column of cells forms a second region of the FET and can be used as a bit line for the entire column. In one embodiment, separate contacts are provided for each of the emitter regions and each of the FET gate regions, while in another embodiment, only a single contact to both of the emitter region and FET gate region of each cell is required.

Charge injector transistor memory

An improved composite channel field effect transistor and method of fabrication, which exhibits high density characteristics and yields high performance with less sensivity to threshold shift due to hot electrons when operated at high source to drain voltage levels.

Composite channel field effect transistor and method of fabrication

An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.

High reliability, low leakage, self-aligned silicon gate FET and method

A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate region has a threshold voltage determined by an impurity imparted thereto by either diffusion or ion implantation. The third or storage region has a lower threshold voltage than the gate region. A single unitary metal electrode extends in superimposed relation to the second and third regions. Upon the application of potentials to the first region and the electrode, charge carriers may be stored in or removed from the third region so as to write a '1' or a '0' in the cell.

Single-electrode charge-coupled random access memory cell with impurity

An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, ##EQU1## AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS C.sub.P =.sqroot.C.sub.(P.sub.-1) .sup.. C.sub.(P.sub.+1). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.

Optimal driver for LSI

A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate region has a predetermined threshold voltage and the third or storage region has a lower threshold voltage. A single unitary metal electrode extends in superimposed relation to the second and third regions. Upon the application of potentials to the first region and the electrode, charge carriers may be stored in or removed from the third region so as to write a '1' or a '0' in the cell.

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Poughkeepsie, NY, United States of America

Irving T Ho