Other

International Business Machines Corporation

Infineon Technologies Ag

Infineon Technologies North America Corp.

Irene Lennox McStay

Helmut Horst Tews

Stephan Kudelka

Rajarao Jammy

Uwe Schroeder

Jack Allan Mandelman

Oleg Gluschenkov

Michael Patrick Chudzik

Johnathan E Faltermeier

Kwong Hon Wong

Ashima B Chakravarti

Porshia Shane Wrschka

Stephen Rahn

Lawrence Alfred Clevenger

Carl John Radens

Ramachandra Divakaruni

Rolf Weis

Bernhard Sell

Matthias Goldbach

Rama Divakaruni

Larry Alan Nesbit

Harald Seidl

Joseph Francis Shepard, Jr

Uwe Paul Schroeder

Kenneth T Settlemyer, Jr

Andreas Knorr

Satya N Chakravarti

Mihel Seitz

Dirk Schumann

Kil-Ho Lee

Jean-Marc Rousseau

Manfred Hauf

A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench. The oxide layer and the nitride layer is then removed from the lower portion. Finally, the lower portion of the trench is processed selectively to nitride, e.g. by one or more capacitor forming processes, and then the upper portion of the trench is processed.

Sacrificial collar method for improved deep trench processing

A method and structure for increasing the area and capacitance of both trench and planar integrated circuit capacitors uses Si nodules deposited on a thin dielectric seeding layer that is absorbed during subsequent thermal processing, thereby avoiding a high resistance layer in the capacitor.

Method of area enhancement in capacitor plates

Control of separation between transfer gate and storage node in vertical DRAM

Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

Low resistivity deep trench fill for DRAM and EDRAM applications

A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

Method for surface roughness enhancement in semiconductor capacitor manufacturing

An apparatus ( ) and method for depositing material on a semiconductor wafer with non-planar structures ( ). The wafer ( ) is positioned in a chamber ( ), and reactive gases ( ) are introduced into the chamber ( ). The gases ( ) and wafer ( ) are heated, wherein the gas ( ) temperature in the process chamber ( ) and in the vicinity of the wafer ( ) surface is lower than the temperature of the wafer ( ) surface. A material is deposited on the wafer ( ) surface using chemical vapor deposition. A gas cooler may be utilized to lower the temperature of the reactive gases ( ) while the wafer ( ) is heated.

RTCVD process and reactor for improved conformality and step-coverage

Rough oxide hard mask for DT surface area enhancement for DT DRAM

Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

Process flow for capacitance enhancement in a DRAM trench

A process for forming a sacrificial collar on the top portion of a deep trench ( ) of a semiconductor wafer ( ). A nitride layer ( ) is deposited within the trenches ( ). A semiconductor material layer ( ) is deposited over the nitride layer ( ) and is etched back to a predetermined height (A) below the substrate 112 top surface. A semiconductor material plug ( ) is formed at the top surface of the recessed semiconductor material layer ( ), leaving a void ( ) in the bottom of each trench ( ). An oxide layer ( ) and nitride layer ( ) are formed over the wafer ( ) and trenches ( ), and the semiconductor material plug ( ) and semiconductor material layer ( ) are removed from the bottom of the trenches ( ).

Process flow for sacrificial collar with polysilicon void

A compact resistor is formed in an integrated circuit using many of the same steps as are employed in forming a trench capacitor for a DRAM cell; in particular depositing a layer of heavily doped germanium in the trench interior after the step of doping the substrate to form the bottom plate for the capacitor, depositing polysilicon having the required resistivity in the trench then removing the germanium and leaving only enough to form an ohmic contact in the trench bottom.

Simultaneous formation of deep trench capacitor and resistor

A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation

A process for forming a sacrificial collar ( ) on the top portion of a deep trench ( ). A nitride layer ( ) is deposited within the trench ( ). A semiconductor layer ( ) is deposited over the nitride layer ( ). A top portion of the semiconductor layer ( ) is doped to form doped semiconductor layer ( ). Undoped portions ( ) of the semiconductor layer are removed, and the doped semiconductor layer ( ) is used to pattern the nitride layer ( ), removing the lower portion of nitride layer ( ) from within deep trenches ( ) and leaving a sacrificial collar ( ) at the top of the trenches ( ).

Process flow for sacrificial collar with poly mask

A gate structure for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer on a semiconductor substrate, over which a polysilicon gate electrode is formed. The gate structure further includes a gate conductor that is electrically connected with the gate electrode through a diffusion barrier layer having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.

Semi-insulating diffusion barrier for low-resistivity gate conductors

A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

Method of forming self-limiting polysilicon LOCOS for DRAM cell

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Hopewell Junction, NY, United States of America

Irene Lennox McStay