Intel Corporation

Iqbal Rajwani

Altug Koker

Sanjeev S Jahagirdar

Bhushan M Borole

Anupama Ambardar Thaploo

Lakshminarayanan Striramassarma

Varghese George

Josh B Mastronarde

Vikranth Vemulapalli

Naveen Matam

Lance Cheney

Melaku Teshome

Eric Finley

Binoj Xavier

Abhishek R Appu

Kamal Sinha

Sunil Nekkanti

Ram K Krishnamurthy

Muhammad M Khellah

Steven Hsu

Wenyin Fu

Amit Agarwal

Simeon Realov

Nikos Kaburlasos

Jaydeep P Kulkarni

Eric A Karl

Pascal Meinerzhagen

Kyung-Hoae Koo

Bee Ngo

Charles Augustine

Andrew M Lines

Satish K Damaraju

Somnath Paul

Turbo Majumder

Stephen Kim

Gururaj Shamanna

Lei Jiang

Eric Kwesi Donkoh

Naveen Kumar M

Jagadeesh Chandra Salaka

Surya Sasi Kiran Tallapragada

Daivik H Bhatt

Sravan K Puchakayala

Suphachai Chai Sutanthavibul

Circuits for optimizing the duration of a sense amp enable signal in a memory device such as SRAM.

Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

Enabling product SKUs based on chiplet configurations

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Disaggregation of system-on-chip (SOC) architecture

Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.

Energy efficient memory array with optimized burst read and write data access

Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

Dynamic power budget allocation in multi-processor system

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Disaggregation of System-On-Chip (SOC) architecture

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

Enabling product SKUS based on chiplet configurations

In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

System, apparatus and method for segmenting a memory array

In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

System, apparatus and method for providing a local clock signal for a memory array

Disaggregation of SOC architecture

Growing community of inventors

Roseville, CA, United States of America

Iqbal Rajwani