Oracle International Corporation

Sun Microsystems, Inc.

Ioannis Orginos

Hoyeol Cho

Pangjie Xu

Daniel Fung

Jinho Kwack

Mamun Rashid

Mark E Steigerwald

Systems, methods, and other embodiments associated with using a local voltage regulator embedded within a memory sub-array are described. In one embodiment, a memory device includes a memory sub-array including a set of memory cells and a local voltage regulator. The local voltage regulator is configured to generate a local voltage for powering the memory sub-array. The memory device includes switch logic connected to the memory sub-array and configured to select between the local voltage and a source voltage to power the memory sub-array. The source voltage is provided to the memory device by a host device.

Memory power selection using local voltage regulators

Embodiments provide centralized redundancy block repair for memory circuits. Certain embodiments are implemented in context of high-performance memory, such as last-level cache design, where the primary memory bank often uses high-density memory cells ('bitcells') and supports long self-bitline structures to increase compactness. In such contexts, it can be difficult to finish read operations within a single cycle, even when the entire cache is divided into small bank pieces. Bank-interleaved structure in clusters can be implemented to allow access to different memory banks in consecutive cycles, thereby achieving overall single circle throughput (i.e., the latency can be masked by the interleaving). Accordingly, some embodiments of the centralized block repair can support bank interleaved access, for example, with a strict single-cycle throughput. Some embodiments can also support other features, such as row repair and/or column repair.

Centralized memory repair block

Systems, methods, and other embodiments associated with speculating whether a read request will cause an access to a memory are described. In one embodiment, a method includes detecting, in a memory, a read request from a processor and speculating whether the read request will cause an access to a memory bank in the memory based, at least in part, on an address identified by the read request. The method selectively enables power to the memory bank in the memory based, at least in part, on speculating whether the read request will cause an access to the memory bank.

Speculation to selectively enable power in a memory

Systems, methods, and other embodiments associated with bit line equalization are described. Systems and methods described herein provide secondary bit line equalization for embedded memory systems to reduce equalization time and improve memory performance. The reduction in equalization time is accomplished by adding a secondary equalizer in addition to a standard primary equalizer for a column of memory cells.

Secondary bit line equalizer

Systems and methods are described herein that reduce the read latency of a cache by separating read and write column select signals that cause the cache to initiate certain read and write operations, respectively.

Separate read/write column select control

An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A redundant array includes a CAM array that includes a plurality of memory cells. The CAM array is addressed by the address of a defective memory location within the primary memory array and provides a match identification and a resource identification. The redundant array also includes a translation array wherein an offset to configure an input/output multiplexer is stored. The redundant array also includes a redundant data array including a plurality of memory cells wherein one or more memory cells of the redundant data array are used instead of one or more defective memory cells of the primary array.

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Sunnyvale, CA, United States of America

Ioannis Orginos