International Business Machines Corporation

Globalfoundries Inc.

Ioana C Graur

Lars W Liebmann

Scott Marshall Mansfield

Mark Alan Lavin

Carlos A Fonseca

Young O Kim

Geng Han

Maharaj Mukherjee

Alan Edward Rosenbluth

Kafai Lai

Scott David Halle

Rama Nand Singh

Todd Christopher Bailey

Derren Neylon Dunn

Scott Josef Bukofsky

Dmitry A Vengertsev

Azalia A Krasnoperova

Marshal A Miller

James A Culp

James Allan Bruce

Michael E Scaman

Alfred K Wong

Kriteshwar Kaur Kohli

Gregory J Dick

Ian P Stobert

Zachary Baum

Amr Y Abdo

Ronald L Gordon

Jaione Tirapu Azpiroz

Aditya Chaudhary

Kalpesh G Dave

Gerald Galan

Scott M Mansfiled

Mark N Jobes

Mini M Ghosal

Bhavani P Kumar

Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (OPC). Methods according to the disclosure can include: fabricating a circuit using a proposed IC layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (SRAF) from the proposed IC layout; determining the predicting as being correct when the fabricated circuit includes the printed SRAF, or as being incorrect when the fabricated circuit does not include the printed SRAF; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.

Creating knowledge base for optical proximity correction to reduce sub-resolution assist feature printing

A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Process-metrology reproducibility bands for lithographic photomasks

Systems, methods, and computer program products for design rules checking in which the waiver of design rules is optimized while ensuring compliant designs that are manufacturable. A first design rule and a plurality of patterns of a layout that violate the first design rule are received by a design rule waiver system. The design rule waiver system may process the first design rule to extract a plurality of descriptors that can be perturbed. The design rule waiver system may perturb an attribute associated with at least one of the plurality of descriptors extracted from the first design rule in order to define a second design rule that is satisfied by the plurality of patterns.

Expansion of allowed design rule space by waiving benign geometries

A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single test pattern. Exposure and development equipment performs a single exposure and development process of the single test pattern to produce a single test photoresist. The processor analyzes the single test photoresist to determine which of the size and spacing parameters are unacceptable and which are acceptable, based on differences between the single test photoresist and a model photoresist that the test portion of the integrated circuit design without the SRAFs would produce. The processor adds SRAFs having the acceptable size and spacing parameters to the remaining portion of the integrated circuit design.

Test patterns for determining sizing and spacing of sub-resolution assist features (SRAFs)

Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

Generative learning for realistic and ground rule clean hot spot synthesis

Design errors generated employing a mask rule check (MRC) program are indexed and examined one by one by an automated computer program connected to a false error pattern database that contains previously known waivered patterns, a real error pattern database that contains previously known pairs of an error-containing pattern and a corresponding error-free pattern, and optionally a mask house rule database. A waiver is applied to each design error for which a matching pattern is found in the false error pattern database. Each design error for which a match is found in the real error pattern database is modified to substitute an error-free pattern for an error-containing pattern therein. The output of the automated program includes a list of design errors for which no solution is found by the automated program.

Photomask error correction

Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.

Pattern improvement in multiprocess patterning

Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

Decomposition with multiple exposures in a process window based OPC flow using tolerance bands

A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter that span the range from a predetermined minimum and maximum value of the model parameter. The bin values may be incremented uniformly between the maximum and minimum parameter values, or may be distributed according to a weighting. The lithographic model is calibrated to an initial calibration test pattern. The resulting simulated calibration pattern is evaluated to determine whether the model parameter space is adequately populated. If the parameter space is over or under populated, the calibration pattern is modified until the calibration pattern test values adequately populate the parameter space, so that the final calibrated lithographic process model will more reliably predict images over the full range of image parameters.

Calibration of lithographic process models

Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.

Photomask design verification

Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; categorizing the window area; selecting a solution, from a library of pre-computed solutions, based on a category of the window area; and applying the solution to the hot spot. A service-oriented architecture (SOA) system that synchronizes the design to the process is also provided.

Short path customized mask correction

Modeling of lithographic processes for use in the design of photomasks for the manufacture of semiconductor integrated circuits, and particularly to the modeling of the complex effects due to interaction of the illuminating light with the mask topography, is provided. An isofield perturbation to a thin mask representation of the mask is provided by determining, for the components of the illumination, differences between the electric field on a feature edge having finite thickness and on the corresponding feature edge of a thin mask representation. An isofield perturbation is obtained from a weighted coherent combination of the differences for each illumination polarization. The electric field of a mask having topographic edges is represented by combining a thin mask representation with the isofield perturbation applied to each edge of the mask.

Efficient isotropic modeling approach to incorporate electromagnetic effects into lithographic process simulations

Embodiments of the present invention provide a method of performing printability verification of a mask layout. The method includes creating one or more tight clusters; computing a set of process parameters associated with a point on said mask; comparing said set of process parameters to said one or more tight clusters; and reporting an error when at least one of said process parameters is away from said one or more tight clusters.

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Poughkeepsie, NY, United States of America

Ioana C Graur