Seagate Technology Incorporated

Seagate Technologies, Inc.

Insik Jin

Wei Tian

Venugopalan Vaithyanathan

Dimitar Velikov Dimitrov

Haiwen Xi

Song Sheng Xue

Nurul Amin

Yong Lu

Michael Xuefei Tang

Ming Sun

Hongyue Liu

Chulmin Jung

Youngpil Kim

Yang Li

Harry Hongyue Liu

Zheng Gao

Xiaobin Wang

Brian Lee

Dadi Setiadi

Young Pil Kim

Lance Eugene Stover

Venkatram Venkatasamy

Richard P Larson

Christina L Hutchinson

Eileen Yan

Kaizhong Gao

Antoine Khoueir

Andrew D Habermas

Paul E Anderson

Philip George Pitcher

Shuiyuan Huang

Pat J Ryan

Jaewoo Nam

Shaoping Li

Dexin Wang

Andreas Karl Roelofs

Andrew John Carter

Markus Siegert

Cedric Bedoya

Andrew James Wirebaugh

Declan Macken

Hai Li

Sining Mao

Olle Gunnar Heinonen

Housan Dakroub

John D Stricklin

Daniel Paul Burbank

Thomas Roy Boonstra

Robert William Lamberton

Johannes Van Ek

Ivan Petrov Ivanov

Xuefei Tang

Muralikrishnan Balakrishnan

Markus Jan Peter Siegert

Jeffrey Howard Lake

Hyung-Kew Lee

Mallika Roy

Venu Vaithyanathan

Kenneth P Naughton

William Bruce Fitzpatrick

Andrew Wirebaugh

A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.

Method of switching out-of-plane magnetic tunnel junction cells

Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Programmable metallization memory cell with layered solid electrolyte structure

Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.

Magnetic memory with separate read and write paths

A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.

Tunneling transistors

Nonvolatile resistive memory devices are disclosed. In some embodiments, the memory devices comprise multilayer structures including electrodes, one or more resistive storage layers, and separation layers. The separation layers insulate the resistive storage layers to prevent charge leakage from the storage layers and allow for the use of thin resistive storage layers. In some embodiments, the nonvolatile resistive memory device includes a metallic multilayer comprising two metallic layers about an interlayer. A dopant at an interface of the interlayer and metallic layers can provide a switchable electric field within the multilayer.

Nonvolatile resistive memory devices

A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation.

Single line MRAM

A magnetic memory element that has a stress-induced magnetic anisotropy. The memory element has a ferromagnetic free layer having a switchable magnetization orientation switchable, a ferromagnetic reference layer having a pinned magnetization orientation, and a non-magnetic spacer layer therebetween. The free layer may be circular, essentially circular or nearly circular.

Memory cell with stress-induced anisotropy

A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Magnet-assisted transistor devices

An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel.

Programmable metallization cell switch and memory units containing the same

An example memory cell may have at least a tunneling region disposed between a conducting region and a metal region, wherein the tunneling region can have at least an active interface region disposed between a first tunneling barrier and a second tunneling barrier. A high resistive film is formed in the active interface region with migration of ions from both the metal and conducting regions responsive to a write current to program the memory cell to a selected resistive state.

Non-volatile memory with active ionic interface region

Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations.

Magnetic field assisted stram cells

A non-volatile memory cell that includes a first electrode; a second electrode; and an electrical contact region that electrically connects the first electrode and the second electrode, the electrical contact region has a end portion and a continuous side portion, and together, the end portion and the continuous side portion form an open cavity, wherein the memory cell has a high resistance state and a low resistance state that can be switched by applying a voltage across the first electrode and the second electrode.

Nano-dimensional non-volatile memory cells

Growing community of inventors

Eagan, MN, United States of America

Insik Jin