International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Injo Ok

Soon-Cheon Seo

Balasubramanian Pranatharthiharan

Choonghyun Lee

Charan V V S Surisetty

Alexander Reznicek

Seyoung Kim

Kevin W Brew

Charan V Surisetty

Nicole A Saulnier

Charan Veera Venkata Satya Surisetty

Youngseok Kim

Tenko Yamashita

Timothy Mathew Philip

Wei Wang

Iqbal Rashid Saraf

Sivananda K Kanakasabapathy

Su Chen Fan

Andrew Mark Greene

Jin Ping Han

Ruilong Xie

Takashi Ando

Oleg Gluschenkov

Sanjay C Mehta

Andrew Herbert Simon

Muthumanickam Sankarapandian

Chanro Park

Johnathan E Faltermeier

Matthew Joseph BrightSky

Myung-Hee Na

Steven Michael McDermott

Kangguo Cheng

Chih-Chao Yang

Brent A Anderson

Theodorus E Standaert

Shogo Mochizuki

Michael Rizzolo

Ruqiang Bao

Hsueh-Chung Chen

Yann Mignot

Robert L Bruce

Hao Tang

Kisup Chung

Ching-Tzu Chen

Prasad Bhosale

Balasubramanian Pranatharthi Haran

Lawrence Alfred Clevenger

Lars W Liebmann

Wenyu Xu

Praneet Adusumilli

Min Gyu Sung

Ravikumar Ramachandran

Emre Alptekin

Lan Yu

Adra Carr

Mickey H Yu

Hari Prasad Amanapu

Victor W C Chan

Sungjae Lee

Mary Claire Silvestre

Samuel Sung Shik Choi

Steven M Mcdermott

A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

Antenna assisted ReRAM formation

A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a 'horizontal' portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

Phase change memory programming current leakage reduction

A computer memory device includes a bottom electrode, a top electrode, and a memory component arranged between the top electrode and the bottom electrode. The memory component is made of a dielectric solid-state material and is in direct contact with the top electrode and the bottom electrode. The computer memory device further includes a proximity heater configured to increase a temperature of a portion of the memory component. The computer memory device further includes a layer of dielectric material in direct contact with the proximity heater. The layer of dielectric material is in direct contact with one of the bottom electrode and the top electrode.

Proximity heater to lower RRAM forming voltage

Arrays of PCM devices and techniques for fabrication thereof having an integrated resistor formed during heater patterning for uniform voltage drop amongst the PCM devices are provided. In one aspect, a PCM device includes: at least one PCM cell including a phase change material disposed on a heater; and at least one resistor in series with the at least one PCM cell, wherein the at least one resistor includes a same combination of materials as the heater. A memory array and a method of forming a PCM device are also provided.

Uniform voltage drop in arrays of memory devices

A PCM cell includes a first electrode, a heater/PCM portion electrically connected to first electrode, the heater/PCM portion comprising a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the projection liner. The stack includes a plurality of first layers comprised of a first material and having a plurality of first inner sides facing towards the projection liner, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers comprised of a second material that is different from the first material, and the second plurality of layers having a plurality of second inner sides facing towards the projection liner. The plurality of second inner sides that are offset from the plurality of first inner sides forming a plurality of gaps.

Phase change memory gaps

A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.

Phase change memory using multiple phase change layers and multiple heat conductors

A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.

Phase change memory cell with double active volume

A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

Vertical field effect transistor with low-resistance bottom source-drain contact

An integrated circuit includes a field effect transistor (FET) and a phase change memory (PCM) cell. The PCM cell includes a heater, wherein a bottom surface of the heater is at or below a top surface of the FET.

Heater for phase change material memory cell

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Back end of line embedded RRAM structure with grain growth enhancement

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Back end of line embedded RRAM structure with low forming voltage

A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

Wrap-around projection liner for AI device

A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.

Confined bridge cell phase change memory

An approach to provide a semiconductor structure for a phase change memory cell with a first liner material surrounding a sidewall of a hole in a dielectric material where the hole in the dielectric is on a bottom electrode in the dielectric material. The semiconductor structure includes a layer of a second liner material on the first liner material, where the second liner material has an improved contact resistance to a phase change material. The semiconductor structure includes the phase change material abutting the layer of the second liner material on the first liner material. The phase change material fills the hole in the dielectric material. The second liner material that is between the phase change material and the first liner material provides a lower contact resistivity with the phase change material in the crystalline phase than the first liner material.

Contact resistance of a metal liner in a phase change memory cell

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