International Business Machines Corporation

Elpis Technologies Inc.

Screen Spe USA LLC

Indira P Seshadri

Ekmini Anuja De Silva

Nelson M Felix

Jing Guo

Fee Li Lie

Stuart A Sieg

Gauri V Karve

Leigh Anne H Clevenger

Lawrence Alfred Clevenger

Praveen Joseph

Ruilong Xie

Eric R Miller

Nicole A Saulnier

Tao Li

Mona Abdulkhaleg Ebrish

Ruqiang Bao

Su Chen Fan

Yann Mignot

Christopher Joseph Waskiewicz

Romain Lallement

Isabel Cristina Chu

Nicolas J Loubet

Andrew Mark Greene

Muthumanickam Sankarapandian

Deepika Priyadarshini

Brent A Anderson

Junli Wang

Chen Zhang

Hemanth Jagannathan

Sivananda K Kanakasabapathy

Wenyu Xu

Hosadurga K Shobha

Ardasheir Rahman

Kisup Chung

Siva Kanakasabapathy

Dechao Guo

Zhenxing Bi

Soon-Cheon Seo

John Ryan Sporre

Ashim Dutta

Dario Leonardo Goldfarb

Karen Elizabeth Petrillo

Tsung-Sheng Kang

Eric Miller

Kangguo Cheng

Veeraraghavan S Basker

Carl John Radens

Shogo Mochizuki

Oleg Gluschenkov

Julien Frougier

Terence B Hook

Jingyun Zhang

Hsueh-Chung Chen

Chi-Chun Liu

Joshua M Rubin

Daniel Sanders

Albert M Young

Hoa D Truong

Adra Carr

Kristin Schmidt

Abraham Arceo De La Pena

Yasir Sulehria

Shanti Pancharatnam

Shravana Kumar Katakam

Jon Fayad

Luciana Meli-Thompson

Dustin Wayne Janes

Eric Evans

Domenico DiPaola

A microelectronic device includes a first source and drain structure adjacent to a second source and drain structure. A first conductive contact is in contact with a top surface and side surface of the first source and drain structure. A second conductive contact is in contact with a top surface and side surface of the second source and drain structure. The second conductive contact includes a via extension to connect to a backside component. A separating layer is located between the first conductive contact and the second conductive contact. A first sidewall of the separating layer is flush with the first conductive contact. A second sidewall of the separating layer is flush with the second conductive contact.

Fork sheet device with wrapped source and drain contact to prevent NFET to PFET contact shortage in a tight space

The embodiments herein describe a crossbar VFET where the crossbar channel (or fin) that extends between a pair of channels (fins) has reduced corner rounding, or no corner rounding. This can be achieved by developing a masking feature before etching the channels in the VFET that results in reduced, or no corner rounding in the channel structure etched using the masking feature.

Cross bar vertical FETs

Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.

Vertically stacked fin semiconductor devices

An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

Electronic devices with a low dielectric constant

A method for forming a planarization layer is provided that can include depositing an organic planarization layer on a deposition surface using a spin on deposition method; and treating the deposited organic planarization layer with a solvent anneal. In some embodiments, a vapor of solvent is passed over the deposited organic planarization layer to increase uniformity of the deposited organic planarization layer. The method may further include curing the deposited organic planarization layer with a thermal anneal.

Solvent annealing of an organic planarization layer

A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.

Bottom contact for stacked GAA FET

Embodiments of the invention include a dielectric reflow technique for boundary control in which a first layer is deposited on a first transistor region and a second transistor region, the first and second transistor regions being adjacent. A dielectric layer is formed to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location. In response to removing a portion of the first layer on the first transistor region, the dielectric layer protecting the second transistor region is reflowed such that at least a reflowed portion of the dielectric layer extends beyond the first location.

Dielectric reflow for boundary control

A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

High aspect ratio contact structure with multiple metal stacks

Embodiments disclosed herein include a semiconductor structure for reducing contact to contact shorting. The semiconductor structure may include a gate cut region with a liner and a dielectric core confined within a first lateral side of the liner and a second lateral side of the liner. The semiconductor structure may also include a first source/drain (S/D) contact overlapping the first lateral side and the dielectric core. The first S/D may include a line-end that contacts the second lateral side of the liner.

Source/drain contact positioning under power rail

A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Bottom source/drain etch with fin-cut-last-VTFET

A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.

Vertical field effect transistor with crosslink fin arrangement

The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.

Metal cut patterning and etching to minimize interlayer dielectric layer loss

A semiconductor device is provided. The semiconductor device includes a bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer, the gate stack including a work function metal (WFM) layer, a channel fin formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed in a gate landing area over the gate stack, a second ILD layer formed in an area other than the gate landing area, and a WFM encapsulation layer formed between the first ILD layer and the second ILD layer, and formed on sidewalls of the gate stack.

Vertical transport field-effect transistor with gate patterning

An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

Vertical FET with contact to gate above active fin

Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

Transistor boundary protection using reversible crosslinking reflow

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Troy, NY, United States of America

Indira P Seshadri