Samsung Electronics Co., Ltd.

Inchan Hwang

Byounghak Hong

Seunghyun Song

Kang-Ill Seo

Hwichan Jun

Seungchan Yun

Saehan Park

Seungyoung Lee

Daewon Ha

Harsono S Simka

Kang-ill Seo

Hoonseok Seo

Kang Ill Seo

Jeonghyuk Yim

Gunho Jo

Rebecca Park

Wonhyuk Hong

Ming He

Jaemyung Choi

Hyoeun Park

Myunghoon Jung

JaeHyun Park

Jaejik Baek

Mehdi Saremi

Methods of forming an integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stack structures. The first and second sacrificial stack structures may contact the first and second active regions, and the first and second sacrificial stack structures may each include a channel layer and a sacrificial layer. The methods may also include forming an etch stop layer on the isolation layer, replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, forming a front contact including a front contact plug, forming a back-side insulator, and forming a back contact plug in the isolation layer and the back-side insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.

Integrated circuit devices including backside power rail and methods of forming the same

A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

Three-dimensional semiconductor device having vertical misalignment

An integrated circuit includes a first semiconductor device and a second semiconductor device adjacent to the first semiconductor device. Each of the first and second semiconductor devices includes a lower transistor and an upper transistor on the lower transistor, and the upper and lower transistors each include a source region, a drain region, and a channel region extending between the source region and the drain region. The integrated circuit also includes a first dielectric spacer extending along an inner sidewall of the channel region of the upper and/or lower transistor of the first semiconductor device, a second dielectric spacer facing the first dielectric spacer and extending along an inner sidewall of the channel region of the upper and/or lower transistor of the second semiconductor device. The integrated circuit also includes an interconnect contact between the first semiconductor device and the second semiconductor device.

Limited lateral growth of S/D epi by outer dielectric layer in 3-dimensional stacked device

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods

Integrated circuit devices including a metal resistor and methods of forming the same are provided. The integrated circuit devices may include a substrate including a first surface and a second surface that is opposite the first surface and is parallel to the first surface, a transistor including a gate electrode, first and second resistor contacts that are spaced apart from each other in a horizontal direction that is parallel to the second surface of the substrate, and a metal resistor. The first surface of the substrate may face the gate electrode. The metal resistor may include a third surface and a fourth surface that is parallel to the third surface and the second surface of the substrate, and the fourth surface of the metal resistor may be closer to the second surface than the first surface and contacts the first and second resistor contacts.

Integrated circuit devices including a metal resistor and methods of forming the same

Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

Resistor structures of integrated circuit devices including stacked transistors and methods of forming the same

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a static random access memory (SRAM) unit. The SRAM unit may include a first inverter on a substrate and a power distribution network (PDN) structure including a first power rail and a second power rail. The substrate may extend between the first inverter and the PDN structure. The first inverter may include a first upper transistor including a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor and including a first lower source/drain region, a first power contact extending through the substrate and electrically connecting the first upper source/drain region to the first power rail, and a second power contact extending through the substrate and electrically connecting the first lower source/drain region to the second power rail.

Integrated circuit devices including a power distribution network and methods of forming the same

A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

Selective double diffusion break structures for multi-stack semiconductor device

A semiconductor device including a wafer, a first semiconductor device and a second semiconductor device on a front side of the wafer, power rails on a back side of the wafer, a backside power distribution network (PDN) grid on the back side of the wafer, and front-side signal routing lines above the first and second semiconductor devices on the front side of the wafer. The second semiconductor device is stacked on the first semiconductor device, the backside PDN grid is coupled to the power rails, and the power rails are coupled to the first and second semiconductor devices.

Stacked device with backside power distribution network and method of manufacturing the same

A semiconductor device includes a substrate; a 1transistor formed above the substrate, and having a 1transistor stack including a plurality of 1channel structures, a 1gate structure surrounding the 1channel structures, and 1and 2source/drain regions at both ends of the 1transistor stack in a 1channel length direction; and a 2transistor formed above the 1transistor in a vertical direction, and having a 2transistor stack including a plurality of 2channel structures, a 2gate structure surrounding the 2channel structures, and 3and 4source/drain regions at both ends of the 2transistor stack in a 2channel length direction, wherein the 3source/drain region does not vertically overlap the 1source/drain region or the 2source/drain region, and the 4source/drain region does not vertically overlap the 1source/drain region or the 2source/drain region.

Crossing multi-stack nanosheet structure and method of manufacturing the same

A stacked semiconductor device includes: a substrate; a 1transistor formed on a substrate, and including a 1active region surrounded by a 1gate structure and 1source/drain regions; and a 2transistor stacked on the 1transistor, and including a 2active region surrounded by a 2gate structure and 2source/drain regions, wherein the 1active region and the 1gate structure are vertically mirror-symmetric to the 2active region and the 2gate structure, respectively, with respect to a virtual plane therebetween.

Stacked semiconductor device having mirror-symmetric pattern

A semiconductor device including a static random access memory (SRAM) in a three-dimensional (3D) stack is provided. The semiconductor device includes a first transistor stack including a first channel and a first gate, a second transistor stack including a second channel and a second gate, the second transistor stack being disposed above the first transistor stack, a bit line disposed on a first portion of an upper surface of the first channel, a voltage source disposed on a first portion of an upper surface of the second channel and a first shared contact connecting the first channel to the second channel, where a width of the second channel is less than a width of the first channel.

SRAM memory cell for stacked transistors with different channel width

A semiconductor device include: a substrate; a 1transistor formed above the substrate, the 1transistor including a 1channel set of a plurality of 1nanosheet layers, a 1gate structure surrounding the 1nanosheet layers, and 1and 2source/drain regions at both ends of the 1channel set; and a 2transistor formed above the 1transistor in a vertical direction, the 2transistor including a 2channel set of a plurality of 2nanosheet layers, a 2gate structure surrounding the 2nanosheet layers, and 3and 4source/drain regions at both ends of the 2channel set, wherein the 1channel set has a greater width than the 2channel set, wherein a number of the 1nanosheet layers is smaller than a number of the 2nanosheet layers, and wherein a sum of effective channel widths of the 1nanosheet layers is substantially equal to a sum of effective channel width of the 2nanosheet layers.

Semiconductor device having stepped multi-stack transistor structure

An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

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Schenectady, NY, United States of America

Inchan Hwang