Samsung Electronics Co., Ltd.

In-Young Lee

Hyun-Soo Chung

Ho-jin Lee

Tae-Je Cho

Dong-Hyeon Jang

Hyunsoo Chung

Dong-ho Lee

Ju-Il Choi

Myeong-Soon Park

Tae-young Kim

Young-hee Song

Sang-wook Park

Min-Soo Kim

Tae-Young Kim

Taeje Cho

Seung-Kwan Ryu

Sang-Hoon Choi

Son-Kwan Hwang

Son-kwan Hwang

Sung-min Sim

Jongyeon Kim

Jae-Sik Chung

Nam-seog Kim

Chan-Ho Lee

Chajea Jo

Sang-Uk Han

Cha-Jea Jo

Sang-Sick Park

Yoon-jae Lee

Ji-seok Hong

Seungduk Baek

Dong-hyeon Jang

Seok-Ho Kim

Yong-Chai Kwon

Chang-Woo Shin

Jong-youn Kim

Hae-Jung Yu

Ki-Kwon Jeong

Hyun-Jun Kim

Chang-Seong Jeon

Min-Seung Yoon

Wonkeun Kim

Jung-Seok Ahn

Eun-Kyoung Choi

Han-Sung Ryu

Moon Gi Cho

Myung-Kee Chung

Chang-Cheol Lee

Chee-Hwan Yang

Keum-hee Ma

Byoung-Soo Kwak

Brian Cheon

Won-Seok Jeong

Jin-Kuk Bae

Dong-hyun Jang

A semiconductor chip includes a substrate having a low-k material layer. An electrode pad is disposed the substrate. A first protection layer at least partially surrounds the electrode pad. The first protection layer includes a first opening at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protection layer at least partially surrounds the buffer pad. The second protection layer includes a second opening at an upper portion thereof. A pillar layer and a solder layer are sequentially stacked on the buffer pad. A thickness of the buffer pad is greater than a thickness of the electrode pad. A width of the first opening in a first direction parallel to an upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction.

Semiconductor chip including a bump structure and semiconductor package including the same

An antenna device implemented to prevent the deterioration in radiation performance due to a metal mechanical part and an electronic device including the same is provided. The electronic device includes a metal member in a shape of a loop that is disposed in at least one area of the electronic device and a substrate (printed circuit board (PCB)) for supplying power to a preset location of the metal member in order to use the metal member as an antenna radiator, wherein at least one location of the metal member that differs from the power-supplied location is grounded through the substrate.

Antenna device and electronic device including same

A dipole antenna module and an electronic apparatus include an antenna element, a power feeder formed at an end of the antenna element and connected to a circuit board to process an antenna signal through a cable, and a ground part to ground a ground of the cable such that the ground part keeps a preset gap from the antenna element and is grounded to a conductor of the circuit board.

Dipole antenna module and electronic apparatus including the same

Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

Semiconductor packages having through electrodes and methods of fabricating the same

Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.

Method of manufacturing semiconductor package

Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer.

Semiconductor packages having through electrodes and methods for fabricating the same

Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern.

Semiconductor package and method of fabricating the same

A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip.

Semiconductor device and method of fabricating the same

A semiconductor package and a method of fabricating the same. The method may include mounting a lower stack including a plurality of lower semiconductor chips on a substrate and mounting an upper stack including a plurality of upper semiconductor chips on the lower stack. According to example embodiments of the inventive concept, the semiconductor package can be easily fabricated.

Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Semiconductor packages including a heat spreader and methods of forming the same

A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

Semiconductor package including semiconductor chip with through opening

A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Wafer-level stack package and method of fabricating the same

A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided.

Semiconductor chip, method of fabricating the same, and stack module and memory card including the same

A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug.

Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same

Growing community of inventors

Yongin-si, South Korea

In-Young Lee