Skhynix Inc.

In Soo Lee

Jung Hyuk Yoon

Yoon Jae Shin

Chang Yong Ahn

Jun Ho Cheon

Ji Hyae Bae

A first impedance calibration part configured to perform a first impedance calibration operation of generating a first impedance calibration code set for adjusting an impedance of a first terminating resistor to a first target value, with reference to an external resistor having a first resistance value. A second impedance calibration part configured to perform a second impedance calibration operation of generating a second impedance calibration code set for adjusting an impedance of a second terminating resistor to a second target value, with reference to a reference resistance unit, a resistance value of which is set to a second resistance value according to a part of the first impedance calibration code set.

Impedance calibration circuit, memory controller including the impedance calibration circuit and memory system including the memory controller

A nonvolatile memory apparatus includes a plurality of cell arrays, each including a near area and a far area. A plurality of memory cells are included in the near area, and a plurality of memory cells are included in the far area. When a memory cell of the plurality of memory cells, included in a near area of at least one cell array, among the plurality of cell arrays, is selected, based on an address signal, the nonvolatile memory apparatus selects memory cells included in far areas of the remaining cell arrays based on the address signal. The nonvolatile memory apparatus performs a first read operation on the selected memory cell of the at least one cell array, and performs a second read operation on the selected memory cells of the remaining cell arrays.

Nonvolatile memory apparatus and memory system using the same

A phase change memory device may include a cross point array and a sensing circuit block. The cross point array may include a plurality of word lines, a plurality of bit lines and phase change memory cells. The word lines and the bit lines may intersect each other. The phase change memory cells are positioned at intersection points between the word lines and the bit lines. The sensing circuit block reads data in the phase change memory cells. The sensing circuit block may include a first sensing unit and a second sensing unit. The first sensing unit senses the data using a first voltage. The second sensing unit senses the data using a second voltage, which may be higher than a threshold voltage of the phase change memory cell, when the data in the phase change memory cell read by the first sensing unit is determined to be abnormal.

Cross point array type phase change memory device and method of driving the same

A phase changeable memory device may include a plurality of word lines, a plurality of bit lines, a memory cell, at least one source line, and a discharge unit. The bit lines may cross the word lines. The memory cell may include access elements connected with the at least one source line. The source line may be connected with the access elements. The discharge unit may be connected with a bit line. The discharge unit may be configured to discharge a voltage of the bit line to a ground terminal in response to a signal of the source line. The discharge unit may include a phase changeable material.

Phase changeable memory device having a cross point array structure

A semiconductor memory device includes a plurality of first memory cells included in a first memory cell group and coupled to a plurality of first bit lines, respectively, a plurality of first switches coupled to the first bit lines, respectively, and coupled to a voltage node, a driver configured to supply a constant voltage to the voltage node for a write operation, and a switch control unit configured to selectively turn on one or more of the first switches when the write operation is performed.

Semiconductor memory device including switches for selectively turning on bit lines

Provided is a nonvolatile memory apparatus which writes data into a memory cell according to a program and verify (PNV) operation, wherein the nonvolatile memory apparatus performs the PNV operation for first data during a first time, and performs a plurality of PNV operations for second data during the first time.

Nonvolatile memory apparatus, operating method thereof, and data processing system having the same

A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.

Growing community of inventors

Icheon-si, South Korea

In Soo Lee