Nvidia Corporation

Sun Microsystems, Inc.

Oracle America, Inc.

Ilyas Elkin

Ge Yang

Wojciech Jakub Poppe

Jonah Matthew Alben

Xi Zhang

William James Dally

Puneet Gupta

Robert Paul Masleid

Stuart F Oberman

Ishwardutt Parulkar

Abhishek Ranjan Singh

Ming Yiu Siu

Josephus Ebergen

Bo Tang

Bryan Catanzaro

Georgios K Konstadinidis

Matthew Rudolph Fojtik

Jiani Yu

Yanqing Zhang

Rajarshi Roy

Jonathan Raiman

Neel Kant

Saad Godil

Robert Kirby

Apparatuses, systems, and techniques for designing a data path circuit such as a parallel prefix circuit with reinforcement learning are described. A method can include receiving a first design state of a data path circuit, inputting the first design state of the data path circuit into a machine learning model, and performing reinforcement learning using the machine learning model to output a final design state of the data path circuit, wherein the final design state of the data path circuit has decreased area, power consumption and/or delay as compared to conventionally designed data path circuits.

Data path circuit design using reinforcement learning

An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.

Full adder cell with improved power efficiency

An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

Low power flip-flop element with gated clock

A system including a series of partial product select encoders and partial product muxes, each of the partial product select encoders receiving a multiplier, receiving a carry input from a multiplier tree, and outputting a select signal to an associated partial product mux based on the multiplier and carry input, and each of the partial product muxes outputting a partial product based on the select signal and a multiplicand received.

Radix-4 multiplier partial product generation with improved area and power

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Efficient scan latch systems and methods

A method for operating a latch and a latch circuit are disclosed. The latch circuit comprises a storage sub-circuit, a propagation sub-circuit, and a shared clock-enabled transistor. The storage sub-circuit is configured to capture a level of an input signal when a clock signal transitions from first level to a second level and hold the captured level to generate an output signal while the clock signal is at the second level. The propagation sub-circuit is configured to enable a path through a blocking transistor to the shared clock-enabled supply node to propagate the captured level of the input signal to the storage sub-circuit. The shared clock-enabled transistor is configured to couple the shared clock-enabled supply node to a power supply while the clock signal is at the first level and decouple the shared clock-enabled supply node from the power supply while the clock signal is at the second level.

Latch and flip-flop circuits with shared clock-enabled supply nodes

Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.

Via resistance analysis systems and methods

A method, in one embodiment, can include modeling and calibrating two types of sensors that are part of a semiconductor device. In addition, the method can include determining a temperature and voltage based on data received from the two sensors.

Determining on-chip voltage and temperature

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Low power master-slave flip-flop

The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominant impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominant characteristic oscillating rings, wherein each respective one of the plurality of dominant characteristic oscillating rings includes a respective dominant characteristic. Additional analysis can be performed correlating the dominant characteristic delay impact results with device fabrication and operation.

Coupling resistance and capacitance analysis systems and methods

One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

Latch circuit with a bridging device

Systems and methods for transition delay measuring are presented. A transition delay measuring method can include oscillating a signal between states and tracking an indication associated with an isolated attribute of the transitions between the states. Oscillations can include asymmetric transitions between the states and the tracked isolated attribute can be a delay in completing transitions between the states in one direction or vice versa. The asymmetric transitions can include transitions between the first state and the second state that are faster than slower transitions between the second state and the first state or vice versa. The tracked indication can be utilized in analysis of the isolated transition delay characteristics. The results can be utilized in analysis of various further features and characteristics (e.g., examination of leakage current related power consumption, timing of asymmetric operation, etc.). The analysis can include examination of fabrication process and operating parameters.

Growing community of inventors

Sunnyvale, CA, United States of America

Ilyas Elkin