Texas Instruments Corporation

Ih-Chin Chen

Amitava Chatterjee

Mark Stephen Rodder

Mahalingam Nandakumar

Somnath S Nag

Clarence W Teng

Hisashi Shichijo

Bing W Shen

Theodore Warren Houston

Rick L Wise

Robert R Doering

Hong Yang

Keith Alan Joyner

Purnendu K Mozumder

Jeffrey A McKee

Sreenath Unnikrishnan

Karthik Vasanth

Peter S McAnally

Katherine E Violette

Yin Hu

Iqbal Ali

Jiann Liu

James G Bohlman

Chih-Ping Chao

Hun-Lian Tsai

Agerico L Esquirel

Jerry C Hu

A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region () and a second doped region () underlying the first doped region. A source and drain () are formed adjacent to the channel. In one embodiment of the present invention, the first doped region () is doped with arsenic, while the second doped region () is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer () allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.

Dual-counterdoped channel field effect transistor and method

A system for producing metal gate MOSFETs having relatively low threshold voltages is disclosed, comprising the steps of forming a gate oxide layer on a semiconductor substrate, forming a dummy gate on the substrate, removing the dummy gate after further processing and depositing a lower metallic gate material on said gate oxide; treating the semiconductor device with a reducing gas immediately after deposition of the lower metallic gate material, and depositing an upper gate metal over the lower gate material.

Hydrogen treatment for threshold voltage shift of metal gate MOSFET devices

A trench isolation structure including high density plasma enchanced silicon dioxide trench filling (,) with chemical mechanical polishing removal of non-trench oxide.

Integrated circuit insulator and method

A trench isolation structure can be formed in a stack trench capacitor fabrication process by forming a trench region (,) through a buffer layer (,) and an interface layer (,) and into a semiconductor substrate (,). A trench wall layer (,) is grown on inner walls of the trench region (,) and in contact with the interface layer (,). A trench filler layer (,) is formed on the buffer layer (,) and on the trench wall layer (,) within the trench region (,). The trench filler layer (,) is removed from the buffer layer (,) but remains within the trench region (,). A storage dielectric (,) is deposited on the buffer layer (,) and on the trench filler layer (,) within the trench region (,). A field plate layer (,) is deposited on the storage dielectric (,) and within the trench region (,). The field plate layer (,), the storage dielectric (,), the buffer layer (,), and the interface layer (,) lying outside the trench region (,) are removed. A trench cap layer (,) is formed on the semiconductor substrate (,) such that the trench filler layer (,), the storage dielectric (,) and the field plate layer (,) within the trench region (,) are surrounded by the trench wall layer (,) and the trench cap layer (,) in order to form the trench isolation structure. The trench isolation structure can be used for inter-active region and inter-well isolation.

Method of forming a trench isolation structure in a stack trench capacitor fabrication process

Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.

Integrated circuit and method

A low power transistor (,&prime;) formed in a face of a semiconductor layer (,) of a first conductivity type. The transistor includes a source and drain regions (,) of a second conductivity type formed in the face of the semiconductor layer, and a gate (,) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (,&prime;) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (,&prime;) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (,&prime;).

Semiconductor devices with pocket implant and counter doping

A method of forming a field effect transistor with source and drain on an insulator includes forming a first void region (11) in the outer surface of a semiconductor body (10) and forming a second void region (11) in the outer surface of a semiconductor body. The first void region is separated from the second void region by a portion of the semiconductor body (10). The method further includes depositing a dielectric material in the first void region to form a first insulating region (16) and depositing a dielectric material in the second void region to form a second insulating region (16). The method further includes planarizing the first and second insulating regions to define a planar surface (17). The method also includes forming a conductive source region (34) overlying the first insulating region, forming a conductive drain region (36) overlying the second insulating region, and forming a conductive gate body (24) overlying the planar surface and spaced apart from the conductive source region and the conductive drain region. A field effect transistor device (50) having a substrate (10) is provided. The transistor (50) includes a conductive gate body (24) and a gate insulator layer (32) having a planar outer surface adjacent to the conductive gate body and a planar inner surface (39). The transistor further includes first and second insulating regions (16) formed on the substrate. The transistor (50) also includes a conductive drain region (36) formed on the second insulating region and a conductive source region (34) formed on the first insulating region and spaced apart from the conductive gate body (24) opposite the conductive drain region (36). The conductive drain region and conductive source region define a portion of the planar inner surface (39).

Method for forming planar field effect transistors with source and drain

An isolation trench (60) may comprise a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A protective liner (50) may be formed over the barrier layer (22). The protective liner (50) may comprise a chemically deposited oxide. A high density layer of insulation material (55) may be formed in the trench (20) over the protective liner (50).

Protective liner for isolation trench side walls and method

A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').

A method for forming a transistor (50) includes forming a first insulating region (16) in the outer surface of a semiconductor body (10) and forming a second insulating region (16) in the outer surface of the semiconductor body (10) and spaced apart from the first insulating region by a region of semiconductor material. The method further includes planarizing the first and second insulating regions and the region of semiconductor material to define a planar surface (17) and forming a conductive source region (34) overlying the first insulating region. The method further includes forming a conductive drain region (36) overlying the second insulating region and forming a conductive gate body (24) overlying the planar surface (17) and spaced apart from the conductive source region (34) and the conductive drain region (36). A field effect transistor device (50) having a substrate (10) is provided. The transistor (50) includes a conductive gate body (24) and a gate insulator layer (32) having a planar outer surface adjacent to the conductive gate body and a planar inner surface (39). The transistor further includes first and second insulating regions (16) formed in the substrate. The transistor (50) also includes a conductive drain region (36) formed on the second insulating region and a conductive source region (34) formed on the first insulating region and spaced apart from the conductive gate body (24) opposite the conductive drain region (36). The conductive drain region and conductive source region define a portion of the planar inner surface (39).

A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to 'dishing' that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

Reducing non-uniformity in a refill layer thickness for a semiconductor

A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Multiple substrate bias random access memory device

A non-volatile memory cell structure capable of being programmed by band-to-band tunneling induced substrate hot electron injection is formed in a semiconductor substrate 8 and comprises first 10 and second 12 highly doped regions separated by a channel region 14. A nitride layer 16, such as silicon nitride for example, is formed over the channel region 14. An oxide layer 18, such as silicon dioxide, is then formed over nitride layer. The oxide/nitride layer serves as the floating gate insulator. In another embodiment, an additional oxide layer 15 may be formed between the channel region 14 and the nitride layer 16. The floating gate 20 is formed over the oxide layer 16 and a control gate 24 is insulatively formed over the floating gate 20. Other variations, advantages and a fabrication method are also disclosed.

Non-volatile memory cell with oxide and nitride tunneling layers

A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Method for fabricating a multiple well structure for providing multiple

A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.

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Richardson, TX, United States of America

Ih-Chin Chen