Chartered Semiconductor Manufacturing Ltd (corporation)

Igor V Peidous

Konstantin V Loiko

Elgin Kiok Quek

Vladislav Y Vassiliev

Tan Poh Suan

Chock Hing Gan

Vijai Kumar Chhagan

Guang Ping Hua

Thomas Schuelke

Quek Kiok Boone Elgin

Vijai Kumar N Chhagan

Quek Kiok Elgin

David Yeo Yong Hock

Henry Gerung

Andrew Kuswatno

David Yeo Hock

A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect

A method for making self-aligned sub-micrometer bipolar transistors and FETs on a substrate for BiFET and BiCMOS circuits was achieved using a novel LOCOS structure as a self-aligned implant mask. This LOCOS structure uses a silicon nitride mask comprised of stripes with well defined widths and spacings to form a punchthrough oxide mask of varying thicknesses over the emitter, base, and collector of the bipolar transistor, while providing a thick field oxide elsewhere on the substrate. The oxide mask serves as a self-aligned implant mask for implanting the emitter, base, and collector of the bipolar transistor. The nitride mask can be patterned concurrently to form an implant mask for the FET. A series of ion implants is then used to form the emitter, base, and collector without requiring separate photoresist masks. An array of nitride stripes with well defined widths and spacings can be used to make larger transistors, such as bipolar power transistors. The method for simultaneously forming the bipolar and FET minimizes the thermal budget, and the collector implant can be adjusted to minimize the collector contact resistance. The partially recessed punchthrough oxide around the emitter region reduces the base current, and therefore improves the base transport factor (gain) of the bipolar transistor.

Method and mask structure for self-aligning ion implanting to form various device structures

A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin tapered silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. The taper of the foot provides a gradual increase in mask stiffness as oxidation proceeds under the mask edge, allowing greatest flexibility during the early rapid growth period followed by increasing stiffness during the later stages when the growth rate has slowed, thereby inhibiting the penetration of birds beak. Shear stresses responsible for dislocation generation are reduced by as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of oxide punch though and the narrow oxide thinning effect.

LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect

Method of filling shallow trenches

A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin tapered silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. The taper of the foot provides a gradual increase in mask stiffness as oxidation proceeds under the mask edge, allowing greatest flexibility during the early rapid growth period followed by increasing stiffness during the later stages when the growth rate has slowed, thereby inhibiting the penetration of birds beak. Shear stresses responsible for dislocation generation are reduced by as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of oxide punchthough and the narrow oxide thinning effect.

Locos mask for suppression of narrow space field oxide thinning and

A method for forming a sub-quarter micron MOSFET having an LDD structure is described. An active area is provided in a semiconductor substrate separated from other active areas by isolation regions. Ions are implanted into the semiconductor substrate in the active area wherein a heavily doped region is formed adjacent to the surface of the semiconductor substrate and wherein a lightly doped region is formed underlying the heavily doped region. A first dielectric layer is deposited overlying the semiconductor substrate in the active area. The first dielectric layer is etched away to form an opening to the semiconductor substrate. The semiconductor substrate within the opening is etched through to form a partial trench in the semiconductor substrate. Spacers are formed on the sidewalls of the first dielectric layer within the opening. A layer of conducting material is deposited over the first dielectric layer and the spacers and within the opening. The conducting material is etched to form a gate electrode to complete the fabrication of the integrated circuit device.

Sub-quarter-micron MOSFET and method of its manufacturing

Method and mask structure for self-aligning ion implanting to form

A method to form shallow trench isolation structures with improved isolation fill and surface planarity is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A thin oxide layer is deposited overlying the silicon nitride layer. An isolation trench is etched through the thin oxide layer, the nitride layer, and the pad oxide layer and into the substrate. The silicon nitride layer exposed within the trench is etched to form a lateral undercut leaving a projection of the thin oxide layer and exposing a portion of the underlying pad oxide layer. The thin oxide layer and the exposed portion of the pad oxide layer are etched away thereby exposing portions of the surface of the substrate. A liner oxide is grown on the exposed portions of the semiconductor substrate within the isolation trench and on the surface of the substrate. A layer of isolation dielectric is deposited overlying the liner oxide and the silicon nitride and filling the isolation trench. The isolation dielectric is polished away stopping at the silicon nitride layer. The remaining silicon nitride etched away. The isolation dielectric and the pad oxide are etched away from the surface of the semiconductor substrate. The fabrication of the integrated circuit device is completed.

Method to form shallow trench isolation structures with improved

A method is described for forming MOSFETs with shallow trench isolation wherein the abrupt corners introduced by anisotropically etching the silicon trenches are modified by an oxidation step which rounds off the corners and also reduces the effect of tensile stresses caused by the densified trench filler material. The method selectively exposes the corner regions to an oxidation whereby the formation of an oxide birdsbeak modulates the corners and introduces a compressive stress component in the corner region. Several variations of the procedure are disclosed, including embodiments wherein birdsbeaks extending in both a vertical and horizontal directions from the corners are employed. The channel and gate oxide edges of MOSFETs extend to these corners. By attenuating the abrupt corners and reducing the mechanical stresses, gate oxide integrity is improved and anomalous sub-threshold currents of MOSFETs formed are abated.

Shallow trench isolation of MOSFETS with reduced corner parasitic

Method for making sub-quarter-micron MOSFET

The invention is an improved process for forming isolations of uniform thickness in narrow and wide trenches. The process begins by forming a pad layer on a semiconductor substrate. A first barrier layer is formed on the pad layer. The first barrier layer and pad layer are patterned forming openings, thereby exposing the substrate surface. The substrate is then etched through the openings to form shallow trenches in the substrate. The trenches generally falling into two ranges of width: narrow trenches having widths in the range between 0.3 .mu.m and 1.0 .mu.m; and wide trenches having widths greater than 1.0 .mu.m. A thin oxide film is grown on the sidewalls and bottoms of the trenches. A gap-fill dielectric layer is formed on the thin oxide film. A polysilicon layer is grown on the gap-fill dielectric layer. The polysilicon layer acts as a stop during CMP, providing additional protection of the gap-fill dielectric layer in the wide trenches. A planarizing material layer is formed on the polysilicon layer. The planarizing material layer, polysilicon layer and gap-fill dielectric layer are planarized to the level of the first barrier layer using chemical mechanical polishing (CMP). The residual planarizing material is then stripped. The polysilicon layer is oxidized forming a novel second dielectric oxide layer in an oxidizing atmosphere. The dielectric layer is densified, preferably in the same oxidizing atmosphere, forming an isolation layer with uniform thickness in the narrow trenches and the wide trenches. The stress developed during conversion of the polysilicon layer to a novel second dielectric oxide layer compensates for the stress due to densification of the dielectric layer.

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Singapore, Singapore

Igor V Peidous