International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Globalfoundries U.S. 2 LLC

Marvell International Limited

Globalfoundries U.S. Inc.

Marvell Government Solutions, Llc.

Igor Arsovski

Sebastian Theodore Ventrone

Joseph Andrew Iadanza

Eric D Hunt-Schroeder

Robert Maurice Houle

Michael Thomas Fragano

Hayden C Cranford, Jr

Anthony Richard Bonaccio

Pradeep Thiagarajan

Harold Pilo

Travis Reynold Hebig

Reid A Wistort

Venkatraghavan Bringivijayaraghavan

John Robert Goss

Hemen R Shah

Todd Edwin Leonard

Mark William Kuemerle

Michael Anthony Ziegerhofer

Serafino Bueti

Andrew K Killorin

Jeanne P Bickford

George Maria Braceras

Wei Zhao

Suparna Bhattacharya

Qing Li

Jason Michael Norman

Xiaoli Hu

Arvind Kumar

Thomas M Maffitt

Krishnan Santhana Rengarajan

Susan K Lichtensteiger

Rahul K Nadkarni

Paul J Grzymkowski

Sreejith Chidambaran

Akhilesh Patil

Kerry Bernstein

Todd Alan Christensen

Derick Gardner Behrends

Robert J McMahon

Thomas Gregory Sopchak

Michael Launsbach

Troy Joseph Perry

Deepak I Hanagandi

Arjun Sankar

Navin Agarwal

David M Picozzi

Ranjan B Lokappa

Daniel A Dobson

Matthew W Deming

Darryl R Hill

John Atkinson Fifield

Kirk David Peterson

John Maxwell Cohn

Nazmul Habib

Samuel Scott Adams

Kevin William Gorman

Gary Paul Noble

Nicholas A Polomoff

Vinod Ramadurai

Benjamin T Voegeli

Ezra D B Hall

John B DeForge

Aravindan J Busi

Nathaniel R Chadwick

Alfred Degbotse

Valerie Hornbeck Chickanosky

David J Wager

Xiaoxiao Li

Chao Meng

Bruce Balch

Jieyao Liu

Umberto Garofano

Jeanne H Raymond

Aurelius L Graninger

Kushal Kamal

Hao Pu

Shuangdi Zhao

James A Svarczkopf

Van D Butler

Yuzheng Jin

Kalpesh R Lodha

Hayden (Clay) Cranford, Jr

Joseph A Iandanza

Kyle M Holmes

Rahul K Nadkami

A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.

Multi-port memory architecture for a systolic array

A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

Multi-sense amplifier based access to a single port of a memory cell

Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Customer-transparent logic redundancy for improved yield

The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N&#x2212;of the consecutive read operations, and N is an integer number of the consecutive read operations.

High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read

The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

Sensing circuits for charge trap transistors

A barrier or 'crackstop' that is configured to conduct electrical signals. These configurations may form a wall around integrated, active circuitry of a semiconductor die. This wall may include a conductor that follows a three-dimensional pathway from one side to the other side of the wall. This pathway may have sections that overlap, or double-back, so that portions of the conductor overlap along their individual length. These sections prevent crack propagation internal to the wall.

Hermetic barrier for semiconductor device

Multiple sense amplifier and data path-based pseudo dual port SRAM

An adder includes a primary carry bit generation circuit and a summing circuit. The primary carry bit generation circuit is configured to generate first carry bits for a first number of pairs of bits from first and second operands, and to generate second carry bits for a second number of pairs of bits from the first and second operands. The second number of pairs being different than the first number of pairs. The summing circuit is configured to generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits. The summing circuit is configured to generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

Parallel-prefix adder and method

Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

Ternary content addressable memory

A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.

Multi-port high performance memory

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Memory built-in self test error correcting code (MBIST ECC) for low voltage memories

The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.

Zero test time memory using background built-in self-test

A semiconductor device is disclosed that includes, among other things, a computing device including a plurality of transistors, an activity monitor to determine an activity metric associated with the plurality of transistors, and a power controller to, responsive to the activity metric indicating a first activity level, set a power supply voltage for the plurality of transistors to a first value, and responsive to the activity metric indicating a second activity level less than the first activity level, set the power supply voltage to a second value greater than the first value and apply a first reverse back bias voltage to the plurality of transistors to increase a threshold voltage of the plurality of transistors.

Activity-aware supply voltage and bias voltage compensation

The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

Sequential read mode static random access memory (SRAM)

Growing community of inventors

Williston, VT, United States of America

Igor Arsovski