Nippon Steel Corporation

Ichiro Murai

Kenji Anzai

Tomofune Tani

A semiconductor device comprises a semiconductor substrate of a first conductivity type and a pair of spaced diffused layers of a second conductivity type different from the first conductivity type formed in surface portions of the semiconductor substrate. A gate electrode is formed on a channel region between the pair of diffused layers in the semiconductor substrate with an intermediate gate oxide layer disposed therebetween, and then a silicon dioxide film is formed to cover an upper surface and side surfaces of the gate electrode and surface portions of the substrate in which the pair of diffused layers is formed. A side wall made of polycrystalline silicon is formed to cover the silicon dioxide film on each of the side surfaces of the gate electrode and an interlayer insulating film is formed to cover the silicon dioxide film, the side wall and the substrate. Then, a contact hole is formed through the interlayer insulating film to reach one of the pair of diffused layers, wherein a part of the side wall is exposed within the contact hole and a surface of the exposed part of the side wall is oxidized.

Semiconductor device and method for fabricating same

A semiconductor device including a silicon substrate, an insulator film formed on said substrate, a transistor provided on said insulator film and a capacitor formed in a trench formed in said insulator film, and a method of manufacturing the same.

Semiconductor device having trench type capacitors formed completely

A MOS-type semiconductor device having an LDD structure. The device includes a silicon substrate of a first conductivity type. An insulating film is formed on a main surface of the silicon substrate. A gate electrode made of polycrystalline silicon containing impurities at a first concentration is formed on the insulating film. Sidewall spacers made of polycrystalline silicon containing impurities at a second concentration different from the first concentration are formed at both sides of the gate electrode. Impurity diffusion layers are formed in the main surface of the semiconductor substrate at respective regions thereof where source and drain of the MOS-type semiconductor device are to be formed. Each of the impurity diffusion layers includes a low concentration diffusion layer disposed at a first portion of one of the regions and a high concentration diffusion layer disposed at a second portion other than the first portion of the one region. The first portion extends between a first end substantially corresponding to a side of the gate electrode contiguous with one of the sidewall spacers and a second end substantially corresponding to an outer side of the one sidewall spacer remote from the side of the gate electrode so that a boundary line between the first portion and the second portion is substantially aligned with the outer side of the one sidewall spacer.

MOS semiconductor with LDD structure having gate electrode and side

A contact structure of a semiconductor device comprises a lamination of at least first insulating film, first conductive film and second insulating film formed in that order a through hole formed to penetrate through at least the first insulating film and the first conductive film so that a cross-section of the first conductive film is exposed to the through-hole and a second conductive film formed on an inner surface of the through-hole so that the second conductive film electrically contacts with the cross-section of the first conductive film.

Contact structure of semiconductor device and method of manufacturing

A semiconductor memory device comprising a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having source and drain diffused layers and a gate, an interlayer insulating film covering the MOS transistor, a contact hole formed in the interlayer insulating film so as to reach one of the source and the drain diffused layers, a metallic layer filling up the contact hole and a capacitor formed on the interlayer insulating film and connected electrically to the one diffused layer through the metallic layer.

MOS semiconductor memory device having stack capacitor with metal plug

A semiconductor device applicable to/an SRAM and the like provided with a flip-flop having a pair of transistors and a pair of high resistance loads and a Vcc line connected to the pair of high resistance loads of the flip-flop and holding a power supply voltage is described. The high resistance loads and the Vcc line have a common semiconductor layer which has an concentration of impurities at a portion forming the Vcc line higher than an concentration of impurities of a portion forming the high resistance loads. Furthermore, by forming a conductive layer such as tungsten on the portion of the semiconductor layer where the impurity concentration is high, the Vcc line is formed by the conductive layer or a cooperation of the conductive layer and the semiconductor layer disposed under the conductive layer. By means of such a structure, the Vcc line is surely made low in resistance, and the data access speed is made faster.

Semiconductor SRAM with low resistance power line

A MOS type semiconductor memory device comprises a silicon (Si) substrate of a first conductivity type and a memory cell on a main surface of the Si substrate including a MOS transistor with a first and a second diffused layer highly doped with opposite second conductivity type impurities which provide a source and a drain region spaced apart in the main surface, a gate electrode of a conductive material formed through an insulating layer between the two highly doped diffused layers; an inter-layer insulating film formed to cover the MOS transistor; a capacitor cell formed on the inter-layer film including a lower electrode layer of conductive material formed on the inter-layer insulating film, a portion of which extends through a contact hole formed in the inter-layer insulating layer to penetrate through this layer to reach the junction adjacent to one of the highly doped diffused layers, a dielectric film on the lower electrode layer, and an upper electrode layer formed on the insulating film; and a double-diffused layer doped with the second conductivity type impurities formed to overlap with one of the two highly doped diffused layers at the junction of the Si substrate to make an electric contact between the source-drain circuit of the MOS transistor and the lower electrode.

MOS type semiconductor memory device

A semiconductor memory device including a semiconductor substrate of a first conduction type, a memory cell having a floating gate and a control gate which are formed on a main surface of the semiconductor substrate and stacked with an interlayer insulating film interposed therebetween and having a three-layer structure of an oxide film, a nitride film and another oxide film, a decoder for supplying a voltage to the memory cell, a first well formed on the substrate surface and having a second conduction type different from the first conduction type, and a second well formed in the first well and having the first conduction type, wherein one of the memory cell and the decoder is formed in the second well.

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Tokyo, Japan

Ichiro Murai