Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Electronic Devices & Storage Corporation

Semiconductor Technology Academic Research Center

Ichiro Mizushima

Tsutomu Sato

Hajime Nagano

Yoshitaka Tsunashima

Kiyotaka Miyano

Yoshio Ozawa

Takashi Nakao

Takashi Yamada

Shinichi Nitta

Takashi Suzuki

Shinji Mori

Fumitaka Arai

Katsuyuki Sekine

Akihito Yamamoto

Nobutoshi Aoki

Hisato Oyamatsu

Yuichiro Mitani

Fumiki Aiso

Hirokazu Ishida

Takeo Furuhata

Yoshihiko Saito

Yoshiaki Fukuzumi

Riichiro Shirota

Atsuko Sakata

Masayuki Kitamura

Makoto Mizukami

Hiroshi Itokawa

Masayuki Tanaka

Kyoichi Suguro

Tadashi Sakai

Toshitake Yaegashi

Shinichi Takagi

Akihiro Kajita

Atsushi Yagishita

Mie Matsuo

Masayuki Ichige

Makoto Wada

Yuichi Yamazaki

Toshihiko Iinuma

Naoshi Sakuma

Masayuki Katagiri

Shinichi Nakao

Yasushi Akasaka

Shigehiko Saida

Tsunetoshi Arikado

Osamu Fujii

Masumi Saitoh

Takayuki Ishikawa

Masahiro Kiyotoshi

Shosuke Fujii

Tomohiro Saito

Seiji Inumiya

Kei Watanabe

Atsushi Murakoshi

Koichi Kato

Chika Tanaka

Kenichiro Toratani

Hidenori Miyagawa

Satoshi Matsuda

Kazuya Ohuchi

Hirotaka Nishino

Kazumi Inoh

Junichiro Iba

Katsuya Okumura

Hideaki Aochi

Masaru Kito

Akihiro Kojima

Kazuhiko Yamamoto

Nobuo Hayasaka

Atsuhiro Sato

Satoshi Inaba

Takashi Izumida

Katsuaki Natori

Yoko Iwakaji

Shinji Miyano

Yuuichi Mikata

Miyoko Shimada

Kouji Matsuo

Hiroaki Yamada

Iwao Kunishima

Tokuhisa Ohiwa

Tsukasa Azuma

Satoshi Wakatsuki

Masanobu Miyao

Hiroshi Akahori

Hiroyuki Fukumizu

Hiroki Yamashita

Keisuke Nakazawa

Yoshiharu Takada

Toshiyuki Enda

Yasuhiro Nojiri

Shoji Seta

Hisataka Meguro

Yoshihiro Minami

Hiroyoshi Tanimoto

Moto Yabuki

Masaki Yoshimaru

Kimitoshi Okano

According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

Semiconductor device and dicing method

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Method for manufacturing a semiconductor device

In one embodiment, a method of manufacturing a semiconductor device includes forming a pattern portion and a flat portion on a substrate, the pattern portion including plural patterns, and the flat portion having a flat surface at a position lower than upper surfaces of the patterns. The method further includes transferring a first film on the substrate to continuously form the first film on the upper surfaces of the patterns and on the flat surface of the flat portion and to form a first air gap between the patterns.

Method of manufacturing semiconductor device including air gap between patterns

According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Memory device

In one embodiment, a method of manufacturing a semiconductor device includes forming, on a semiconductor substrate, a sacrificial semiconductor pillar having a pillar-like shape extending in a first direction perpendicular to a main surface of the semiconductor substrate, and being formed of a first semiconductor material. The method further includes forming, around the sacrificial semiconductor pillar, a channel semiconductor layer having a tube-like shape extending in the first direction, and being formed of a second semiconductor material different from the first semiconductor material. The method further includes removing the sacrificial semiconductor pillar after the channel semiconductor layer is formed. The channel semiconductor layer is formed on electrode layers via an insulator, the electrode layers being formed on the semiconductor substrate.

Semiconductor device and method of manufacturing same

A memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Memory device having a stacked variable resistance layer

According to one embodiment, a method of manufacturing a semiconductor device. The method includes introducing an inert gas and a material gas into a predetermined space, applying a voltage to generate plasma in the space after introducing the inert gas and the material gas so as to form a semiconductor layer on a substrate, introducing an oxidation-reduction gas in the predetermined space after the voltage is applied, and stopping the introduction of the material gas, the inert gas, and the oxidation-reduction gas after the voltage is applied.

Method of manufacturing semiconductor device using inert, material, and oxidation-reduction gases

At least first and second SiGe(0&#x2266;x&#x2266;1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second SiGe(0&#x2266;x&#x2266;1) layers. A lattice constant of the first SiGe(0&#x2266;x&#x2266;1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second SiGe(0&#x2266;x&#x2266;1) layer is matched with a lattice constant of the second material layer.

Semiconductor device including a plurality of different functional elements and method of manufacturing the same

In accordance with an embodiment, a semiconductor device includes a substrate, a line-and-space structure, a first film and a second film. The line-and-space structure includes line patterns arranged on the substrate parallel to one another at a predetermined distance. The first film is formed on side surfaces and bottom surfaces of the line patterns by an insulating film material. The second film is formed on the line-and-space structure across a space between the line patterns by a material showing low wettability to the first film. Space between the line patterns includes an air gap in which at least a bottom surface of the first film is totally exposed.

Semiconductor device with air gap therein and manufacturing method thereof

A non-volatile semiconductor memory includes a word line extending in a first direction, a first electrode connected to the word line electrically, an ion diffusion layer with connected to the first electrode electrically, a second electrode connected to the ion diffusion layer electrically and formed of a metal to be diffused into the ion diffusion layer when a positive voltage is supplied thereto, and a bit line extending in a second direction perpendicular to the first direction, the bit line connected to the second electrode electrically. The ion diffusion layer has a first region disposed on the first electrode and a second region disposed between the first region and the second electrode, and the metal is more difficult to diffuse into the second region than into the first region.

Non-volatile semiconductor memory

According to one embodiment, a method for manufacturing a semiconductor device includes: forming a silicon oxide film on a semiconductor substrate; forming a via in the silicon oxide film; forming a contact layer inside the via; forming a silicon layer on the contact layer; and forming a tungsten film embedded in the via by making a tungsten-containing gas react with the silicon layer.

Semiconductor device including a plug and method for manufacturing the same

According to one embodiment, a method for manufacturing a microstructure includes forming a guide film on a patterning material, forming a cured film, forming a mask member, and performing processing of the patterning material using the mask member as a mask. An opening is made in the guide film. An upper surface of the guide film is hydrophilic, a side surface of the opening is hydrophobic. The forming the cured film includes applying a solution to cover the patterning material and the guide film, separating the solution into a hydrophobic block and a hydrophilic block, and curing the solution. The solution contains an amphiphilic polymer having a hydrophobic portion and a hydrophilic portion. A length of the hydrophobic portion is longer than a length of the hydrophilic portion. The mask member is formed by removing the hydrophilic block from the cured film.

Method for manufacturing microstructure using self-assembly of amphiphilic polymer

According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.

Semiconductor device and manufacturing method thereof

A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Nonvolatile semiconductor memory

Growing community of inventors

Yokohama, Japan

Ichiro Mizushima