Nec Corporation

Ichiro Honma

Hirohito Watanabe

Takeshi Okazawa

Hiroki Shirai

Taishi Kubota

Haruhiko Ono

Toshiyuki Hirota

Takashi Sakoh

Masaharu Nakamori

Surface irregularity of a semiconductor device is measured with high accuracy, without being affected by the material properties of a semiconductor film forming the surface. Surface irregularity is evaluated when the semiconductor device is fabricated. This is accomplished using a plate-like element, which has a contact surface brought into contact with the surface of a test specimen. The plate-like element is then moved across the surface of the test specimen by a driving mechanism. The driving mechanism moves either the plate-like element or the test specimen relative to the other. A force caused by the motion is detected, and converted into a parameter equivalent to the friction coefficient between the test specimen and the contact surface. From the friction coefficient, surface irregularity is determined.

Method of evaluating capacitance value of capacitor on semiconductor substrate

A hemispherical grained (HSG) lower electrode, and its manufacturing method, are disclosed in which the yield is enhanced by suppressing the depletion due to insufficient diffusion of an impurity into the hemispherical grains (abbreviated also as HSGs) to reduce the deterioration in the capacity caused by the defect on the negative (lower) electrode side, and preventing the fracture of the HSGs. In a method of forming a capacitor composed of a polysilicon lower electrode, a dielectric film, and an upper electrode, the method of this invention includes at least a step of forming HSG silicon on the lower electrode, where each of its grains has a neck with decreased diameter on the side of the contact plane with the lower electrode, a step of depositing a silicon film covering the HSGs by filling the gaps between the lower electrode in the periphery of the necks and the HSGs while maintaining the rugged shape of the formed HSGs, a step of forming a dielectric film, and a step of forming an upper electrode.

HSG lower electrode structure having a neck supported by a silicon layer

In a method of manufacturing a semiconductor device that has an amorphous-silicon film onto which hemispherical grains are grown, a silicon wafer is cleaned at an elevated temperature using amnmonia hydrogen peroxide water solution, cleaned at an elevated temperature using chlorine hydrogen peroxide water solution, and then immersed in dilute hydrofluoric acid solution, after which it is rinsed with pure water, after which the amorphous-silicon film surface of the wafer is dried using isopropyl alcohol.

Semiconductor cleaning method

After HSG-Si 15,is formed on the surface of a polycrystal silicon film 15, heat treatment is conducted on it using a phosphorus diffusion apparatus in an atmosphere of a mixture gas containing POCl,, O,, and N,gases in such a situation that the O,/POCl,mole ratio is adjusted into 0.2 through 1.5, thus diffusing phosphorus into the HSG-Si 15,. With this, it is possible to suppress the corrosion of silicon by the chlorine radicals and inhibit the accelerated oxidation of silicon, thus preventing the reduction of the HSG-Si 15

Method for manufacturing semiconductor devices

A fabrication method of a semiconductor device is provided, which makes it possible to introduce suitably a dopant into surface grains of a semiconductor layer at a comparatively low temperature. In the first step, a first semiconductor layer is formed over a semiconductor substrate through a first dielectric. In the second step, the first semiconductor layer is heat-treated to form semiconductor grains on a surface of the first semiconductor layer, thereby roughening the surface of the first semiconductor layer. The grains are made of a same material as that of the first semiconductor layer. In the third step, the first semiconductor layer with the semiconductor grains is heat-treated at a temperature of approximately 700&deg; C. to 780&deg; C. for a specific time in an atmosphere containing a gaseous dopant, thereby introducing the dopant into the semiconductor grains of the first semiconductor layer from the atmosphere. Preferably, a step of forming a second dielectric layer is additionally provided between the second and third steps, where the second dielectric layer is not doped with any dopant. The dopant is introduced into the semiconductor grains of the first semiconductor layer through the second dielectric layer in the third step. Thereafter, a step of removing the second dielectric layer is provided after the third step.

Fabrication method of semiconductor device with HSG configuration

A method of forming a silicon layer disclosed herein includes the steps of depositing an amorphous silicon layer on a substrate, irradiating a silane gas to the substrate, and performing an annealing process in a high vacuum or in an inert gas. The amorphous silicon layer is thereby converted into a silicon layer having an uneven surface caused by hemispherical or spherical silicon grains. The annealing process may be performed while irradiating a hydrogen gas or an oxidizing gas. In this case, such a silicon layer that has an even surface is formed.

Method of producing silicon layer having surface controlled to be uneven

There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

Nonvolatile semiconductor memory device and manufacturing method of the

There is disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

A method of manufacturing a semiconductor memory device, comprising the steps of: forming a gate electrode with an insulating spacer, forming a first silicon oxide film by high-temperature chemical vapor deposition (CVD), forming n-type source/drain regions, forming a first insulating interlayer and forming a bit line; forming a second silicon oxide film by low-temperature CVD, forming a BPSG film, and annealing the second silicon oxide film and the BPSG film by first annealing to form a second insulating interlayer constituted by the stacked films; forming a third silicon oxide film by low-temperature CVD, and annealing the third silicon oxide film by second annealing; forming a node contact hole through the annealed third silicon oxide film, the second insulating interlayer, the first insulating interlayer, and the first silicon oxide film; forming an amorphous silicon film doped n-type at the time of the film formation, patterning the amorphous silicon film to form an amorphous silicon film pattern, and removing a native oxide film on a surface of the amorphous silicon film pattern using dilute hydrofluoric acid; and converting the amorphous silicon film pattern into an n-type hemispherical grained (HSG) polysilicon film pattern by third annealing to form a storage node electrode, forming a capacitive dielectric film, and forming a cell plate electrode.

Growing community of inventors

Tokyo, Japan

Ichiro Honma