Lam Research Corporation

Applied Materials, Inc.

Ian J Morey

Janet M Flanner

Susan Ellingboe

Christine M Janowiak

John Lang

Joel M Cook

Linda N Marquez

Helen H Zhu

James R Bowers

Graham W Hills

Rao Annapragada

Michael Goss

Chok Ho

Wayne Babie

Ting Chien

Matt M Hamrah

Method for etching a feature in an integrated circuit wafer with minimized effect of micromasking. The method introduces a flow of etchant gas including a fluorocarbon gas to the wafer, and uses the etchant gas to form a plasma in proximity with at least a portion of the wafer. The plasma is used to etch at least a portion of the feature in the wafer. Disassociation of the fluorocarbon into fluorine and hydrocarbon species performs two functions. The fluorine species prevents or significantly reduces sputtered hardmask components from depositing on the floor of the etched feature during etching. The hydrocarbon species acts to form a passivation layer on the sidewalls of the feature.

Unique process chemistry for etching organic low-k materials

Process for stripping photoresist from a semiconductor wafer formed with at least one layer of OSG dielectric. The stripping process may be formed in situ or ex situ with respect to other integrated circuit fabrication processes. The process includes a reaction may be oxidative or reductive in nature. The oxidative reaction utilizes an oxygen plasma. The reductive reaction utilizes an ammonia plasma. The process of the present invention results in faster ash rates with less damage to the OSG dielectric than previously known stripping methods.

Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications

Techniques for etching through a low capacitance dielectric layer in a plasma processing chamber are disclosed. The techniques uses an etch chemistry that includes N , O , and a hydrocarbon. By etching the low capacitance dielectric layer with a plasma created out of the etch chemistry, fast etch rates can be obtained while also maintaining profile control and preserving critical dimension of the resultant opening (e.g., via/trench) being etched in the low capacitance layer.

Technique for etching a low capacitance dielectric layer

Convertible hot edge ring to improve low-K dielectric etch

Method for stripping photoresist from a semiconductor wafer including a layer of organosilicate dielectric. The method introduces a flow of hydrogen-containing gas to the wafer, and uses the hydrogen-containing gas to form a plasma in proximity with at least a portion of the wafer. The plasma is used to strip at least a portion of the photoresist from the wafer. Where the stripping of the photoresist from the semiconductor wafer is performed subsequent to an etching step performed on the wafer in an etch apparatus, the present invention in turn enables the stripping of the photoresist in situ within the etch apparatus. A surprising result of the present invention is that dramatically elevated concentrations of hydrogen gas not only enable high throughput strip rates, but that the utilization of these highly concentrated hydrogen gas mixtures can be performed in safety.

Post etch photoresist strip with hydrogen for organosilicate glass low-&kgr; etch applications

Method for etching dual damascene structures in organosilicate glass

Two-step process to improve low-K dielectric etch uniformity, apparatus to perform the method, and semiconductor devices formed in accordance with the method. In a first etching step, an insulating hot edge ring is provided. When the photoresist clearing signal is observed using end-point software, the insulating cover is moved aside to expose the conductive edge ring for the remainder of the etch. One aspect of this invention contemplates an insulator cover over a conductive edge ring at the start of wafer etching, which cover is removed after end-pint detection. The present invention contemplates a number of physical configurations whereby the insulator ring is urged into, and away from, its masking of the conductive edge ring. Alternatively, the etching of a wafer bearing low-K material may be conducted using two edge rings, where the first etch step is conducted using an insulating hot edge ring, and a second etch step is conducted using a conductive hot edge ring. According to this aspect, the two step process may thus be performed in a plurality of reactor vessels, or in one reactor vessel having a plurality of processing stations. Different low-K materials may require differing etchant/passivant/diluent combinations. Accordingly, the two-step etch process is taught in conjunction with any number of different etch chemistries.

In a plasma processing chamber, a method for etching through a selected portion of an oxide layer of a wafer's layer stack to create a self-aligned contact opening is described. The wafer stack includes a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above said polysilicon layer and the oxide layer disposed above the nitride layer. The method for etching includes etching through the oxide layer of the layer stack with a chemistry and a set of process parameters. The chemistry essentially includes C.sub.2 HF.sub.5 and CH.sub.2 F.sub.2 and the set of process parameters facilitate etching through the oxide layer without creating a spiked etch and etching the oxide layer through to the substrate without substantially damaging the nitride layer.

Self-aligned contacts for semiconductor device

A method for etching through a low capacitance dielectric layer in a plasma processing chamber. The low capacitance dielectric layer is disposed below a hard mask layer on a substrate. The method includes flowing an etch chemistry that includes N.sub.2 and H.sub.2 into the plasma processing chamber. There is included creating a plasma out of the etch chemistry. The method also includes etching, using the plasma, through the low capacitance dielectric layer through openings in the hard mask layer in the plasma processing chamber.

Techniques for etching a low capacitance dielectric layer on a substrate

The addition of a gaseous source of hydrogen radicals, such as hydrogen, ammonia or methane to oxide RIE etching chemistries, in amounts of from about 5 to about 20 percent by volume of the total gas flow, will increase the oxide etch rate while suppressing the polysilicon etch rate. This effect is more pronounced at lower wafer temperatures. This new process chemistry increases the oxide etch rate to greater than 5000 .ANG./min., improves the selectivity to polysilicon to greater than 25:1 and improves the selectivity to photoresist to greater than 6:1, without having a significant detrimental effect on the profile angle, the RIE lag and the etch rate uniformity. Selectivities of 50:1 have been achieved with less than 15% RIE lag using the chemistry CHF.sub.3, Ar, CF.sub.4 and NH.sub.3, with NH.sub.3 constituting 10 percent by volume of the gas flow.

Growing community of inventors

Singapore, Singapore

Ian J Morey