Micron Technology Incorporated

Ian C Laboriante

Kunal R Parekh

John David Hopkins

Akira Goda

Krishna Kumar Parat

Martin Ceredig Roberts

Justin B Dorhout

Chet E Carter

Kunal Shrotri

Fei Wang

Matthew Park

Vinayak Shamanna

Ryan L Meyer

Ramey M Abdelrahaman

Benben Li

Durai Vishak Nirmal Ramaswamy

Prashant Raghu

Beth R Cook

Wayne H Huang

Lei Bi

Michael Tristan Andreas

Joseph Neil Greeley

Sanjeev Sapra

Jerome A Imonigie

Tom Jibu John

Wei Yeeng Ng

Ho Yee Hui

Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

Multi-decks memory device including inter-deck switches

A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.

Methods of forming an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor

A surface modification composition comprising a silylation agent comprising a silyl acetamide, a silylation catalyst comprising a perfluoro acid anhydride, an amine-based complexing agent, and an organic solvent. Methods of modifying a silicon-based material and methods of forming high aspect ratio structures on a substrate are also disclosed.

Surface modification compositions, methods of modifying silicon-based materials, and methods of forming high aspect ratio structures

A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described.

Methods of forming hydrophobic surfaces on semiconductor device structures, methods of forming semiconductor device structures, and semiconductor device structures

A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material.

Methods of forming a programmable region that comprises a multivalent metal oxide portion and an oxygen containing dielectric portion

Methods of forming a memory cell having programmable material that comprises a multivalent metal oxide portion and an oxygen containing dielectric portion

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Boise, ID, United States of America

Ian C Laboriante