Taiwan Semiconductor Manufacturing Comp. Ltd.

I-Shan Huang

Ling-Sung Wang

Chan-yu Hung

Ru-Shang Hsiao

Wen-Hsi Lee

Ching-Hwanq Su

Ying Hsin Lu

Yu-Jen Chen

Pin Chia Su

Pohan Kung

Li-Yi Chen

Yi-Ju Chen

Sheng-Fu Yu

Chan-Yu Hung

Kuan Yu Chen

A semiconductor structure includes first and second active regions extending in a first direction. The semiconductor structure further includes gate electrodes extending in a second direction perpendicular to the first direction. Each of the gate electrodes includes a first segment over at least one of the first active region or the second active region; a gate extension extending beyond each of the first active region and the second active region, wherein the gate extension has a uniform width in the first direction, and a conductive element, wherein a width of the conductive element in the first direction increases as a distance from the gate extension increases along an entirety of the conductive element in the second direction.

Semiconductor device

A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.

Semiconductor device including unilaterally extending gates and method of forming same

A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

Structure for metal gate electrode and method of fabrication

A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

Metal gate structures and methods of fabricating the same in field-effect transistors

A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.

Semiconductor device including trimmed-gates and method of forming same

A method of making a semiconductor structure includes forming a plurality of gate electrodes over a plurality of active regions. The method further includes increasing a width of a portion of each of the plurality of gate electrodes between adjacent active regions of the plurality of active regions, wherein increasing the width of the portion of each of the plurality of gate electrodes comprises increasing the width of less than an entirety of each of the plurality of gate electrodes between the adjacent active regions. The method further includes removing a central region of each of the plurality of gate electrodes, wherein the central region has the increased width, and removing the central region comprises removing less than an entirety of the portion of each of the plurality of gate electrodes.

Method of making semiconductor device and semiconductor device

A method (of manufacturing a semiconductor device) includes: forming active regions including spacing apart neighboring active regions resulting in corresponding gaps; forming gate structures (overlying the active regions and the gaps) including locating intra-gap segments of the gate structures over the gaps, arranging each intra-gap segment to include two end regions separated by a central region, and at intersections between active regions and gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the two; and removing selected portions of at least some of the intra-gap segments including removing central regions of first selected intra-gap segments substantially without removing portions of corresponding end regions of the first selected intra-gap segments, and removing central regions and portions of end regions of second selected intra-gap segments for which corresponding end regions of the second intra-gap segments abut flyover intersections thereby trimming corresponding gate structures.

Method of forming semiconductor device including trimmed-gates

The semiconductor structure includes first and second active regions arranged in a first grid oriented in a first direction. The semiconductor structure further includes gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction. The first and second active regions are separated, relative to the second direction, by a gap. Each gate electrode includes a first segment and a gate extension. Each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height H, where H&#x2264;150 nanometers (nm). Each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular.

A semiconductor device includes: active regions arranged in a first grid oriented substantially parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction. The first gaps are interspersed correspondingly between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into a corresponding one of the first gaps.

Semiconductor device including trimmed-gates

A semiconductor structure includes: first and second active regions arranged in a first grid oriented in a first direction; and gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction; wherein: the first and second active regions are separated, relative to the second direction, by a gap; each gate electrode includes a first segment and a gate extension; each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height H, where H&#x2264;(&#x2248;150 nm); and each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular. In an embodiment, the height His H&#x2264;(&#x2248;100 nm).

Semiconductor device, corresponding mask and method for generating layout of same

A semiconductor device includes: active regions arranged in a first grid oriented parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction. The first gaps are interspersed between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into the corresponding gap.

Semiconductor device including trimmed-gates and method for generating layout of same

Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided. In one example, a semiconductor device structure includes a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of gate structures includes a first gate structure having a first gate end width and a second gate structure having a second gate end width, wherein the second gate end width is shorter than the first gate end width.

Gate-end structure engineering for semiconductor applications

Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.

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Tainan, Taiwan

I-Shan Huang