Vanguard International Semiconductor Corporation

I-Ping Lee

Erik S Jeng

Eddy Chiang

Fu-Liang Yang

Chih-Cherng Liao

Ya-Ting Chang

Tsung-Hsiung Lee

Tzu-Shih Yen

Kwang-Ming Lin

Yu-Jui Chang

Bih-Tiao Lin

Kai-Chuan Kan

Chyei-Jer Hsieh

Ya-Huei Kuo

Kuei-Chuen Ho

Pei-Yu Chang

Zheng-Xian Wu

Yow-Shiuan Liu

Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.

Methods for forming semiconductor devices

A new method is provided to treat contact holes after hole formation has been completed. A layer of non-conformal dielectric is deposited over the surface in which the contact hole has been formed thereby including the sidewalls and bottom of the contact hole. The non-conformal dielectric will be unevenly deposited on The sidewalls and bottom of the contact hole. This results in a relatively light deposition of non-conformal dielectric along the lower portions of the sidewalls and on the bottom of the contact hole with a heavier coating of non-conformal dielectric being deposited along the upper reaches of the contact hole. The objective of the invention is to prevent the enlargement of the hole diameter during subsequent processing steps. The non-conformal dielectric can be removed from the bottom using a wet etch.

Method of forming contact using non-conformal dielectric liner

A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen. The method may also be employed in general for etching silicon oxide layers in the presence of silicon nitride layers. Similarly, the method may also in general be employed in removing fluorocarbon polymer residue layers from integrated circuit layers including but not limited to silicon oxide layers and silicon nitride layers.

Multiple etch contact etching method incorporating post contact etch etching

A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate. The method comprises the steps of: forming a first dielectric layer over said cell array area and said periphery; forming a plurality of first contact holes through said first dielectric layer in said cell array area and said periphery area, said periphery area including a bitline and a word line, said word line and said bitline being used for addressing said memory cell; forming a first conductive layer in said plurality of first contact holes and on said first dielectric layer; patterning and etching said first conductive layer to form said storage node and said plurality of interconnections simultaneously; forming a second dielectric layer and a second conductive layer subsequently on said first dielectric layer, said storage node and said plurality of interconnections; and patterning and etching said second dielectric layer and said second conductive layer to form a charge storage means and a plurality of contact plugs.

Method for simultaneously fabricating a DRAM capacitor and metal

A method for etching a metal layer on a substrate with dimensional control is disclosed. First, an anti-reflection layer is formed over the metal layer. A photoresist layer is then formed over the anti-reflection layer. A metal layer pattern is defined by patterning the photoresist layer. An etching process is performed to etch the anti-reflection layer with dimensional loss compared with the metal layer pattern, by using the photoresist layer as a mask. Another etching process is performed to etch the metal layer with dimensional gain compared with the anti-reflection layer, by using the anti-reflection layer as a mask. A metal layer with nearly zero-biased dimension is achieved.

Method for etching a metal layer with dimensional control

A new method of etching AlCu or AlSiCu lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A layer of AlCu or AlSiCu is deposited overlying insulating layer. A silicon nitride or titanium nitride/silicon dioxide layer is deposited overlying the metal layer wherein a hard mask is formed. The hard mask is covered with a layer of photoresist which is exposed to actinic light wherein the hard mask prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask. The hard mask is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The AlCu or AlSiCu layer and the barrier layer not covered by the patterned hard mask are etched away to form metal lines having an outwardly tapered profile.

Method of dry etching A1Cu using SiN hard mask

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Taouan, Taiwan

I-Ping Lee