Macronix International Co., Ltd.

I-Jen Huang

Nian-Kai Zous

Yung-Feng Lin

Hsin-Yi Ho

Yin-Jen Chen

Hang-Ting Lue

Shih-Hung Chen

Kuang-Chao Chen

Tuung Luoh

Ling-Wuu Yang

Ta-Hone Yang

Wen Pin Lu

Chi Yuan Chin

Ming Shiang Chen

A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.

Method and system for detecting defects of wafer by wafer sort

A structure of 3D memory comprises a plurality of stacking layers and a plurality of cells. The stacking layers are arranged in a three-dimensional array and disposed parallel to each other on a substrate, and the stacking layers comprises a plurality of stacking memory layers. The cells comprises a first group of cells (such as m of cells) for storing information data and a second group of cells (such as n of cells) for storing ECC (error checking and correcting) spare bits. All of the first group and the second group of cells are read out at the same time for performing an ECC function. The ECC spare bits in the 3D memory according to the present disclosure can be constructed at the same physical layer or at the different physical layers. The embodiments can be implemented, but not limited, by a vertical-gate (VG) structure or a finger VG structure.

Structure of ECC spare bits in 3D memory

A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Multi-bit flash memory and reading method thereof

A method for programming a MLC memory includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+Kand repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL&#x2212;K, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.

Method for programming a multilevel memory

Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage Vis applied to the first group of memory cells Mand M. A second drain voltage Vis applied to the second group of memory cells Mand M, where V=V+&#x394;V. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.

Variable program and program verification methods for a virtual ground memory in easing buried drain contacts

A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+Kand repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL&#x2212;K, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.

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Kaohsiung, Taiwan

I-Jen Huang