Realtek Semiconductor Inc.

I-Hsiu Lo

Yu-Lan Lo

Shu-Yi Kao

Yung-Jen Chen

A circuit verification method, including the following steps: inputting a circuit design data to a processor, wherein the circuit design data includes a plurality of logic circuits and a plurality of detection nodes, each logic circuit includes a control terminal and a plurality of input terminals, and is configured to output a signal to the detection node; inputting a plurality of first-stage property command to the processor to generate a plurality of first-stage formal commands, and the first-stage formal commands are configured to verify whether signals of the detection nodes remain stable when a signals of the control terminal of each of the logic circuits does not changed; finding a first part of the detection nodes by a formal method according to the first-stage formal commands; and finding a second part of the detection nodes by a formal method.

Circuit verification method

A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.

Clock deadlock detecting system, method, and non-transitory computer readable storage medium

A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.

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Hsinchu, Taiwan

I-Hsiu Lo