Lam Research Corporation

Applied Materials, Inc.

Korea Advanced Institute of Science and Technology

Hyungsuk Alexander Yoon

Yezdi N Dordi

Fritz C Redeker

John M Boyd

Andrew D Bailey, Iii

John Boyd

Shijian Li

William Thie

Ming Xi

Mikhail Korolik

Michael Xiaoxuan Yang

Yunsang Kim

Arthur M Howald

Tiruchirapalli Arunagiri

Hongbin Fang

Jason A Ryder

Hui Zhang

Zhongwei Zhu

Ling Chen

Andras Kuthi

Christophe Marcadal

Byung Jin Cho

Michael Xi Yang

Thorsten B Lill

Aleksander Owczarz

Alan M Schoepp

Carl Woods

Yang Pan

David J Hemker

Mark Henry Wilcoxson

John P Parks

Benjamin W Mooring

William T Lee

Sung Gap Im

Soonil Hong

Stephan Hoffmann

Jeffrey G Gasparitsch

Jae Hoon Bong

Fritz Redecker

Onejae Sul

Seong Jun Yoon

Kwanyong Pak

Randy Johnson

A method for fabricating a plurality of resistive random access memory (RRAM) cells includes providing a substrate including a memory medium arranged on an underlying layer; creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm; depositing switching material defining a filament of the RRAM cells in the channel holes; depositing a top electrode of the RRAM cells on the memory medium and the switching material; and separating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes.

Resistive random access memory with preformed filaments

A method of forming ferroelectric hafnium oxide (HfO2) in a substrate processing system includes depositing an HfO2 layer on a substrate, depositing a capping layer on the HfO2 layer, annealing the HfO2 layer and the capping layer to form ferroelectric hafnium HfO2, and selectively etching the capping layer to remove the capping layer without removing the HfO2 layer.

Capping layer for a hafnium oxide-based ferroelectric material

A method of forming ferroelectric hafnium oxide (HfO) in a substrate processing system includes depositing an HfOlayer on a substrate, depositing a hafnium nitride (HfN) layer on the HfOlayer; and annealing the HfOlayer and the HfN layer to form ferroelectric hafnium HfO.

Modifying ferroelectric properties of hafnium oxide with hafnium nitride layers

Provided are methods of sealing open pores of a surface of a porous dielectric material using an initiated chemical vapor deposition (iCVD) process. In one example method of sealing open pores, since the polymer thin film having a significantly thin thickness may be formed by a solvent-free vapor deposition method without plasma treatment, it is possible to minimize deterioration of characteristics of the dielectric material vulnerable to plasma and a chemical solution.

Method of sealing open pores on surface of porous dielectric material using iCVD process

A method for forming nanowire semiconductor devices includes a) providing a substrate including an oxide layer defining vias; and b) depositing nanowires in the vias. The nanowires are made of a material selected from a group consisting of germanium or silicon germanium. The method further includes c) selectively etching back the oxide layer relative to the nanowires to expose upper portions of the nanowires; and d) doping the exposed upper portions of the nanowires using a dopant species.

Methods for forming germanium and silicon germanium nanowire devices

This disclosure relates to a method of manufacturing n-doped graphene and an electrical component using ammonium fluoride (NHF), and to graphene and an electrical component thereby. An example method of manufacturing n-doped graphene includes (a) preparing graphene and ammonium fluoride (NHF); and (b) exposing the graphene to the ammonium fluoride (NHF), wherein through (b), a fluorine layer is formed on part or all of upper and lower surfaces of a graphene layer, and ammonium ions are physisorbed to part or all of the upper and lower surfaces of the graphene layer or defects between carbon atoms of the graphene layer, thereby maintaining or further improving superior electrical properties of graphene including charge mobility while performing n-doping of graphene.

[object Object]

A proximity heads for dispensing reactants and purging gas to deposit a thin film by Atomic Layer Deposition (ALD) includes a plurality of sides. Extending over a portion of the substrate region and being spaced apart from the portion of the substrate region when present, the proximity head is rotatable so as to place each side in a direction of the substrate region, and is disposed in a vacuum chamber coupled to a carrier gas source to sustain a pressure for the proximity head during operation. Each side of the proximity head includes a gas conduit through which the reactant gas and the purging gas are sequentially dispensed, and at least two separate vacuum conduits on each side of the gas conduit to pull excess reactant gas, purging gas, or deposition byproducts from a reaction volume between a surface of the proximity head facing the substrate and the substrate.

Apparatus and method for atomic layer deposition

A cluster architecture and methods for processing a substrate are disclosed. The cluster architecture includes a lab-ambient controlled transfer module that is coupled to one or more wet substrate processing modules. The lab-ambient controlled transfer module and the one or more wet substrate processing modules are configured to manage a first ambient environment. A vacuum transfer module that is coupled to the lab-ambient controlled transfer module and one or more plasma processing modules is also provided. The vacuum transfer module and the one or more plasma processing modules are configured to manage a second ambient environment. And, a controlled ambient transfer module that is coupled to the vacuum transfer module and one or more ambient processing modules is also included. The controlled ambient transfer module and the one or more ambient processing modules are configured to manage a third ambient environment. The cluster architecture therefore enables controlled processing of the substrate in either the first, second or third ambient environments, as well as during associated transitions.

Controlled ambient system for interface engineering

An apparatus generating a plasma for removing fluorinated polymer from a substrate is provided. The apparatus includes a powered electrode assembly, which includes a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The apparatus also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated. The first wire mesh is shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the fluorinated polymer.

Apparatus for the removal of a fluorinated polymer from a substrate

The embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect. The adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided. The method includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method also includes depositing the functionalization layer over the metallic layer in the integrated system. The method further includes depositing the copper layer in the copper interconnect structure in the integrated system after the functionalization layer is deposited over the metallic barrier layer.

Method for barrier interface preparation of copper interconnect

A method for generating plasma for removing metal oxide from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the metal oxide. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an rf field to the cavity using the powered electrode to generate the plasma from the inert and the process gas.

Methods for removing a metal oxide from a substrate

A method of filling of vias and trenches in a dual damascene structure with a filling comprising copper or copper alloy is provided. An electroless deposition filling of the vias with a via filling comprising copper or copper alloy is provided. A trench barrier layer is formed over the via filling with a trench barrier layer comprising Mn or Al. The trench barrier layer is annealed at a temperature that causes a component of the trench barrier layer to pass into the via filling. The trenches are filled with a trench filling comprising copper or copper alloy.

Interconnect with self-formed barrier

Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Methods and apparatuses for three dimensional integrated circuits

A method of depositing a thin film by atomic layer deposition (ALD) on a substrate surface is disclosed. The disclosed method includes placing an ALD deposition proximity head above the substrate with at least one gas channel configured to dispense a gas to an active process region of the substrate surface. The ALD deposition proximity head extends over and is being spaced apart from the active process region of the substrate surface when present. After a pulse of a first reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head, a pulse of a second reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head to react with the first reactant gas to form a portion of the thin layer of ALD film on the surface of substrate underneath the proximity head.

Methods for atomic layer deposition

Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Device with post-contact back end of line through-hole via integration

Growing community of inventors

San Jose, CA, United States of America

Hyungsuk Alexander Yoon