Samsung Electronics Co., Ltd.

Hyunglae Eun

Dong Won Kim

Dong Uk Kim

Inhoon Park

Wonyeoung Jung

Chulseung Lim

Jangseon Park

A storage device includes a non-volatile memory; a volatile memory; and a memory controller configured to control the non-volatile memory and the volatile memory. The memory controller is configured to, in response to a determination that a progressive defect has occurred in at least one memory of the non-volatile memory or the volatile memory during an operation of the storage device, such that the at least one memory is determined to be a defective memory, perform a repair operation on the defective memory based on executing a memory revival firmware.

Memory controllers, storage devices, and operating methods of the storage devices

A test operation condition of a volatile memory device is set such that an error probability is increased based on the test operation condition, compared to a normal operation condition for a normal operation of the volatile memory device. A test mode is set with respect to a test object region corresponding to at least a portion of a memory cell array included in the volatile memory device. A test operation of the volatile memory device is performed based on the test operation condition during the test mode to detect error position information of errors in data stored in the test object region. A runtime repair operation is performed with respect to the volatile memory device based on the error position information.

Method of controlling repair of volatile memory device and storage device performing the same

A method of controlling repair of a volatile memory device, includes, performing a patrol read operation repeatedly to provide error position information of errors included in read data from a volatile memory device, generating accumulated error information by accumulating the error position information based on the patrol read operation performed repeatedly, determining error attribute based on the accumulated error information, the error attribute indicating correlation between the errors and a structure of the volatile memory device, and performing a runtime repair operation with respect to the volatile memory device based on the accumulated error information and the error attribute. The errors may be managed efficiently to prevent failure of the volatile memory device, and thus performance and lifetime of the volatile memory device and the storage device may be enhanced.

A storage device including a nonvolatile memory device, a dynamic random access memory (DRAM) device, and a storage controller, an operation method of the storage device including performing an access operation on the DRAM device, collecting accumulated error information about the DRAM device based on the access operation, detecting a fail row of the DRAM device based on the accumulated error information, and performing a runtime repair operation on the detected fail row.

Storage device that performs runtime repair operation based on accumulated error information and operation method thereof

A memory system includes a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup region, and a memory controller configured to store data to be stored in a plurality of selected memory cells in the plurality of selected memory cells and the backup region, the plurality of selected memory cells being connected to a selected word line of a selected memory device among the plurality of memory devices, and replace the selected word line with a redundancy word line to which a plurality of redundancy memory cells among the plurality of memory cells are connected in response to a correctable error correction code (CECC) occurring in at least one of the plurality of selected memory cells.

Memory systems for performing failover

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit connected between the memory cell array and the ECC engine, an error information register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The control logic circuit controls the ECC engine, the I/O gating circuit and the error information register based on a command and address. The I/O gating circuit provides the ECC engine with codewords which are read from the memory cell array through refresh operations on the plurality of memory cell rows. The ECC engine performs an ECC decoding on main data of the codewords based on parity bits of the codewords and provides error generation signals to the control logic circuit in response to detecting correctable errors with respect to a corresponding address resulting from performing the ECC decoding.

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Seongnam-si, South Korea

Hyunglae Eun