Samsung Electronics Co., Ltd.

Hyung-Shin Kwon

Sung-Bong Kim

Soon-Moon Jung

Joon-Yong Joo

Won-Seok Cho

Hyung-Dong Kim

Jong-Hyoung Lim

Chung-Ki Lee

Kwang-Ok Koh

Chang-Soo Lee

Do-Hyung Kim

Dong-Won Lee

Hong-Sun Hwang

Jun-Beom Park

Seug-Gyu Kim

A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

Semiconductor memory device, method of testing the same and method of operating the same

A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.

Multiple well bias memory

A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Semiconductor devices and methods of manufacturing the same

Methods of manufacturing semiconductor devices

A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch process. The increased height of the cell region spacers is adapted to further prevent over-etching during gate interconnect formation which would otherwise result in etching through the spacer to the substrate and subsequent short circuit. Therefore, it is also possible to prevent bridge defects due to over-etching, which occurs because the barrier metal layer for a subsequent interconnection contact is accidentally connected to the underlying substrate. Also, since the recessed spacer structure is provided in the peripheral region, it is possible to remarkably enhance a resistance distribution of a cobalt silicide layer occurring in a gate line width of 100 nm or less.

Method of improving gate resistance in a memory array

The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 &#x212b; in the impurity region.

Semiconductor device having silicide thin film and method of forming the same

Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.

Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses

An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof

The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided. Further, the method includes defining an active region a semiconductor substrate, forming a gate electrode crossing over the active region, sequentially stacking first and second insulating layer patterns an active region adjacent to opposite sides of the gate electrode, forming a silicon epitaxial layer on the active region to be adjacent to edges of the first and second insulating layer patterns, and siliciding at least a part of the silicon epitaxial layer. The edge of the first insulating layer pattern contacting the active region is protruded from the edge of the second insulating layer pattern, and the silicon epitaxial layer covers the protruded edge of the first insulating layer pattern.

Method of fabricating a semiconductor device having an elevated source/drain

Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.

Methods of fabricating semiconductor devices having gate insulating layers with differing thicknesses

Semiconductor device having elevated source/drain

An interconnection structure is provided by foiling a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

Unitary interconnection structures integral with a dielectric layer

The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 &angst; in the impurity region.

A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are sequentially stacked on a predetermined region of a semiconductor substrate. Impurities are implanted into the semiconductor substrate to form a source/drain region. A first metal silicide layer is selectively formed on the surface of the source/drain region. The silicidation resistant layer pattern is then removed to expose the gate electrode. A second metal silicide layer is selectively formed on the exposed gate electrode. Consequently, the first metal silicide layer can be formed of a metal silicide layer having superior tolerance with respect to junction spiking. Also, the second metal silicide layer can be formed of another metal silicide layer having a low variation of resistivity due to the variation of the line width of the gate electrode. Therefore, it is possible to fabricate a high-performance MOS transistor suitable for a highly integrated semiconductor device.

Method for fabricating a MOS transistor using a self-aligned silicide technique

The present invention provides a method of forming a semiconductor device spacer. In the method, a gate pattern is formed on a semiconductor substrate, and a first insulation layer, a second insulation layer, and a third insulation layer are sequentially formed over substantially the entire surface of the resultant structure. The second and third insulation layers are formed of the same material under a first pressure and a second pressure higher than the first pressure, respectively, and preferably of silicon nitride, using a low pressure chemical vapor deposition (LPCVD) technique. The third and second insulation layers are sequentially, anisotropically etched until the first insulation layer is exposed, thereby forming a spacer and a second insulation pattern. The spacer is selectively removed by an isotropic etching method, to minimize the recessed extent of the second insulation pattern. The exposed first insulation layer is etched to form a first insulation pattern.

Growing community of inventors

Kyunggi-do, South Korea

Hyung-Shin Kwon