Samsung Electronics Co., Ltd.

Hyung-joon Kwon

Jong-Chul Park

Myung-Hoon Jung

Woo-cheol Lee

Il-man Bae

Tokashiki Ken

Sang-min Lee

Myeong-Cheol Kim

Ki-Joon Kim

Gwang-Hyun Baek

Chang-Woo Sun

Shin Kwon

Hak-sun Lee

Hye-Ji Yoon

Eun-Sun Noh

Chae-Lyoung Kim

Magnetic devices, and methods of manufacturing the same, include a stack structure including at least one magnetic layer, etched using an etching gas including at least 70 volume percent of a hydrogen-containing gas and at least 2 volume percent of CO gas.

Magnetic devices and methods of manufacturing the same

In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures. Each MTJ structure includes a sequentially stacked first magnetic layer pattern, tunnel layer pattern, and second magnetic layer pattern, and each of the MTJ structures contacts a corresponding one of the lower electrodes.

Methods of manufacturing a magnetoresistive random access memory device

In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.

Methods of manufacturing magnetoresistive random access memory devices

A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of Hgas.

Magnetic device and method of manufacturing the same

A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.

Magnetic device having a metallic glass alloy

A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Memory device for use in high-speed block pipelined reed-solomon decoder, method of accessing the memory device, and reed-solomon decoder having the memory device

A method and system for error correcting C/PI words using error locations detected by EFM/EFM+ decoder are provided. The method for channel decoding and error correcting includes: (a) setting up a channel code; (b) producing demodulated data including information data symbols and erasure flags by modulating channel data symbols, using the channel code; and (c) performing an error-erasure correction on the information data symbols of the demodulated data, using error locations indicated by the erasure flags. The system for channel decoding and error correcting includes a channel decoder with a channel code for producing the demodulated data having the information data symbols and the erasure flags by demodulating the channel data symbols, a memory for storing the demodulated data, and a decoding unit for performing an error-erasure correction on the information data symbols, using the error locations indicated by the erasure flags having a predetermined value.

Method and apparatus for correcting C1/PI word errors using error locations detected by EFM/EFM+ decoding

A pattern buffer apparatus for a dynamic write strategy, which buffers non return to zero (NRZ) data patterns in order to generate a recording pulse in a compact disc system, includes a pattern detector which detects a pattern edge and a pattern from the NRZ data; a write address generating unit which generates a write address indicating a pattern buffer which stores the pattern in response to a write enable signal; the pattern buffer which has a plurality of registers and stores the detected pattern according to the write address; and a read address generating unit which generates a read address in response to a read enable signal, and reads the current pattern stored in the pattern buffer indicated by the read address.

Minimum delay buffering method, minimum delay buffer device for dynamic write strategy, and CD-RW/DVD-RW system having the same

Memory device for use in high-speed block pipelined Reed-Solomon decoder, method of accessing the memory device, and Reed-Solomon decoder having the memory device

A Galois field processor having a dual parallel data path for a Bose Chaudhuri Hocquenghem/Reed-Solomon (BCH/RS) decoder is provided. The Galois field processor includes a syndrome register block for storing syndrome values transmitted by a syndrome generating block, a correction polynomial register block, a connection polynomial register block, and a discrepancy register block. A dual mode Galois field data path (DMGFDP) includes a first data path for receiving the respective outputs of the syndrome register block, the correction polynomial register block, the connection polynomial register block, and the discrepancy register block, performing predetermined operations related to the even-degree coefficients of correction and connection polynomial, and outputting the even-degree coefficient output. A second data path performs predetermined operations related to the odd-degree coefficients of the correction and connection polynomial and outputs the odd-degree coefficient output. A delta output unit performs predetermined operations related to the even-degree and the odd-degree coefficients of the connections polynomial and outputs the delta output. An output unit outputs the coefficients of an error location polynomial, according to a control signal. Since the Galois processor, in which latency during the operation processes is minimized, has a small area and operates at high speed, the performance of the decoder is greatly improved.

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Seongnam-si, South Korea

Hyung-joon Kwon