Samsung Electronics Co., Ltd.

Other

Hyung Jong Lee

Changseop Yoon

Hyun Jin Kim

Deok Han Bae

Kwangsub Yoon

Jongmil Youn

Deokhan Bae

Boram Im

Juyoun Kim

Jun Seok Choi

Juhun Park

Seo Young Lee

Byung Chan Ryu

Seulgi Yun

Seki Hong

Jong Ho You

Sangyoung Kim

Hyonwook Ra

A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

Semiconductor device and method of fabricating the same

A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Semiconductor device having fin-type active patterns with shared contact plugs

Semiconductor device

Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

Semiconductor devices

A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.

Multi-channel transistor including an asymmetrical source/drain contact

The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.

Methods of manufacturing semiconductor devices

Semiconductor device having shared contact

A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

Semiconductor device and method of manufacturing the same

Provided are a lightwave circuit and a method of manufacturing the same. The lightwave circuit includes a first substrate having an engraved core formation groove which is formed on an upper portion of the first substrate, a core layer which is formed inside the engraved core formation groove, a BPSG bonding layer which is formed on the first substrate including the core layer, and a second substrate which is formed on the BPSG bonding layer. Accordingly, light loss and branching uniformity of the lightwave circuit are effectively improved, and the lightwave circuit is manufactured simply and inexpensively while also further improving light loss and branching uniformity of the lightwave circuit.

Lightwave circuit and method for manufacturing same

Disclosed is an optical module comprising, an optical waveguide on the upper side of a substrate; a cutout with at least two slant surfaces, passing at least the core of the optical waveguide; and a film-filter above the cutout. Constructions of bi-directional multi-wavelength optical transmitter-receiver assembly using the optical module as a unit element are also provided in variety on a planar substrate. According to this invention, a bi-directional multi-wavelength transmitter-receiver, which is compact, reliable, excellent in the optical performance and simple in the alignments between the composing elements, can be produced.

Growing community of inventors

Osan-si, South Korea

Hyung Jong Lee