Samsung Electronics Co., Ltd.

Hyun-Sung Shin

Ik-Joon Choi

So-Young Kim

Jae-Youn Youn

Tae-Kyu Byun

Seung-Man Shin

In-Su Choi

Chan-Kyung Kim

Insu Choi

Dae-Jeong Kim

Sung-Ho Park

Sang-Hoon Shin

Sang-Joon Hwang

Chan-ik Park

Yong-Sik Park

Sang-Hoan Chang

Taek-Soo Kim

Jung-Ho Jung

Seungman Shin

A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.

Memory device supporting skip calculation mode and method of operating the same

A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

Stacked memory device, a system including the same and an associated method

According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.

Memory device scrambling address

A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.

Nonvolatile memory devices, memory systems and methods of operating nonvolatile memory devices for processing user data

A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

A process transmission system comprises a process transmission server and a client device configured to communicate with the process transmission server. The process transmission server receives program request information from the client device, packs a process of a program to generate a process package comprising a central processing unit (CPU) register value associated with the program, and transmits the process package to the client device. The client device transmits program request information to the process transmission server, receives a process package corresponding to the program request information from the process transmission server, and executes a process by performing data processing on the received process package. The data processing comprises storing the process in a main memory device of the client device based on the process package and transmitting the CPU register value to a CPU of the client device.

Systems and methods for updating computing programs

A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

Semiconductor memory device and computer system including the same

An interface circuit includes a deserializer and a frame detection circuit. The deserializer includes a serial input terminal for receiving a serial signal, the serial signal including a frame start code; and a plurality of first output terminals for outputting a plurality of parallel signals based on the received serial signal, one of the plurality of parallel signals being a frame signal including the frame start code. The frame detection circuit is configured to detect the frame signal at one of the output terminals of the plurality of first output terminals.

Interface circuit, interface system and method of interfacing signals transferred between devices

A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.

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Seoul, South Korea

Hyun-Sung Shin