Samsung Electronics Co., Ltd.

Hyun-Jun Sim

In-gyu Baek

Jin-Shi Zhao

Eun-Kyung Yim

Jang-Eun Lee

Dong-Suk Shin

Min-Young Park

Se-Chung Oh

Hong-Sik Yoon

Kyung-Tae Nam

Jun-Ho Jeong

Kook-tae Kim

Jae-young Park

Ho-Sung Son

Sung-Uk Jang

Ju-Ri Lee

Dae-Kyom Kim

Chang-ki Hong

Sun-Young Lee

Sang-Bom Kang

Suk-Hun Choi

Ki-Yeon Park

Yoon-Ho Son

Sun-ghil Lee

Sun-jung Kim

Kang-Hun Moon

Han-ki Lee

Won-Oh Seo

Hyun-seung Kim

Hyun-Deok Yang

Sang-Mi Choi

Xiang-Shu Li

A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.

Methods of fabricating semiconductor devices

A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.

Semiconductor devices and methods of manufacturing the same

In a method of manufacturing a semiconductor device, a preliminary gate insulation layer is formed on a substrate, and at least a portion of the substrate serves as a channel region. A hydrogen plasma treatment is performed on the preliminary gate insulation layer to form a gate insulation layer, and the hydrogen plasma treatment supplying a hydrogen-containing gas and an inert gas supply in a chamber via different gas supply parts to form a hydrogen plasma region and an inert gas plasma region in the chamber, respectively. A gate electrode is formed on the gate insulation layer, and impurity regions are formed at upper portions of the substrate adjacent to the gate electrode.

Methods of manufacturing semiconductor devices that include performing hydrogen plasma treatment on insulating layer

A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Manufacturing method for semiconductor device

A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Nonvolatile memory devices that use resistance materials and internal electrodes

A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse.

Variable resistance memory devices and methods of programming variable resistance memory devices

Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.

Multi-level nonvolatile memory devices using variable resistive elements

Nonvolatile memory devices that use resistance materials and internal electrodes, and related methods and processing systems

Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Methods of forming resistive memory devices

In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact hole. A planarization process is performed on the metal layer until the first insulation layer is exposed to form a first contact. A second contact is grown from the first contact. The second contact is formed without performing a photolithography process and an etching process to prevent misalignments.

Methods of forming a contact structure

Provided is a semiconductor device including a resistive memory element. The semiconductor device includes a substrate and the resistive memory element disposed on the substrate. The resistive memory element has resistance states of a plurality of levels according to generation and dissipation of at least one platinum bridge therein.

Semiconductor devices having resistive memory elements

Resistive memory devices and methods of forming resistive memory devices

Growing community of inventors

Hwaseong-si, South Korea

Hyun-Jun Sim