Electronics and Telecommunications Research Institute

Hyun-cheol Bae

Kwang-Seong Choi

Yong Sung Eom

Jong Tae Moon

Haksun Lee

Jong-Hyun Lee

Jin Ho Lee

Yil Suk Yang

Sang Gi Kim

Moo Jung Chu

Seok-Hwan Moon

Seok Hwan Moon

Jong-Moon Park

Yong-Sung Eom

Jong Il Won

Jung Hyun Noh

Jin-Gun Koo

Ho-eun Bae

KeonSoo Jang

Keon-Soo Jang

Su Jeong Jeon

Ieeseul Jeong

Wagno Alves Braganca Junior

A laser bonding method includes forming a bonding part including an adhesive layer and a conductive particle disposed within the adhesive layer on a substrate; aligning a bonding target by disposing the bonding target on a surface of the bonding part opposite the substrate; disposing a pressing part on a surface of the bonding target that is opposite to the bonding part and pressing the bonding target onto the bonding part through the pressing part; heating the bonding target by irradiating at least the pressing part with a laser and conducting heat from the pressing part to the bonding target and from the bonding target to the bonding part; and bonding together the bonding part and the bonding target by the heat conducted from the bonding target to the bonding part so that the conductive particle electrically connects the substrate and the bonding target. The pressing part may be removed.

Laser bonding method

Provided is a method of fabricating a semiconductor package. The method includes preparing a package substrate having a substrate pad, and mounting a semiconductor chip on the substrate pad. Mounting the semiconductor chip includes forming a resin layer containing a solder and reducing agent granules having a first capsule layer, between a chip pad of the semiconductor chip and the substrate pad, and bonding the chip pad to the substrate pad using laser irradiated to the semiconductor chip.

Method of fabricating a semiconductor package

A pattern-forming method for forming a conductive circuit pattern, the pattern-forming method including the steps of: preparing a pattern-forming composition composed of: Cu powder; solder particles for electrically coupling the Cu powder; a polymer resin; a deforming agent that is selected from among acrylate oligomer, polyglycols, glycerides, polypropylene glycol, dimethyl silicon, simethinecone, tributyl phosphare, and polymethylsiloxane, and that increases bonding force between the Cu powder and the solder particles; a curing agent; and a reductant; forming a circuit pattern by printing the pattern-forming composition on a substrate; heating the circuit pattern at a temperature effective to cure the pattern-forming composition and provide the conductive circuit pattern; and electrolytically plating a metal layer onto the conductive circuit pattern. A circuit pattern having superior conductivity is formed at low cost.

Pattern-forming method for forming a conductive circuit pattern

Provided is a method of fabricating a semiconductor package. The method includes providing a package substrate including a pad, mounting a semiconductor chip with a solder ball on the package substrate to allow the solder ball to be disposed on the pad, filling a space between the package substrate and the semiconductor chip with a underfill resin including a reducing agent comprising a carboxyl group, and irradiating the semiconductor chip with a laser to bond the solder ball to the pad, wherein the bonding of the solder ball to the pad comprises changing a metal oxide layer formed on surfaces of the pad and the solder ball to a metal layer by heat generated by the laser.

Provided is a bonding structure of an electronic equipment including first electrodes extended in a first direction and arranged in a second direction on a stretchable display panel having stretchability, second electrodes extended in a first direction and arranged in a second direction on a substrate and facing the first electrodes, and solder bonding parts interposed between the first electrodes and the second electrodes, facing each other in the second direction, and constituting a plurality of rows in the first direction.

Bonding structure of electronic equipment

Provided is a semiconductor device. The semiconductor device includes: a first semiconductor layer having a first region with a first device and a second region with a second device; a device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device from each other; a drain provided on a lower surface of the first region of the first semiconductor layer; and a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer.

Semiconductor device and method of fabricating the same

A method of fabricating a solder-on-pad structure is provided. The method may include providing a substrate with a pad, coating a solder bump maker including a first resin and a solder powder on the substrate, heating the solder bump maker to a temperature lower than a melting point of the solder powder to aggregate the solder powder on the pad, and removing the first resin.

Method of fabricating a solder-on-pad structure and flip-chip bonding method using the same

Provided are methods of forming a bump and a semiconductor device with the same. The method may include providing a substrate with pads, forming a bump maker layer to cover the pads and include a resin and solder particles, thermally treating the bump maker layer to aggregate the solder particles onto the pads, removing the resin to expose the aggregated solder particles, forming a resin layer to cover the aggregated solder particles, and reflowing the aggregated solder particles to form bumps on the pads.

Methods of forming bump and semiconductor device with the same

Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.

Silicon interposer including backside inductor

Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber.

Vacuum wafer level packaging method for micro electro mechanical system device

Provided is an electronic device that includes an LTCC inductor including a first sheet disposed on a substrate and including a first conductive pattern, a second sheet disposed on the first sheet and including a second conductive pattern, and a via electrically connecting the first conductive pattern to the second conductive pattern, and a spacer disposed on a lower surface of the first sheet to provide an air gap between the substrate and the first sheet, wherein the first conductive pattern is exposed out of the lower surface of the first sheet.

Electronic device including LTCC inductor

A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.

Growing community of inventors

Daejeon, South Korea

Hyun-cheol Bae