Advanced Semiconductor Engineering, Inc.

Hyeongno Kim

Sangbae Park

Junyoung Yang

HyungJun Park

YongGil Lee

KyungSoo Rho

JinHee Won

Kun-A Kang

Hyung Jun Park

Junhong Lee

Bae Doo Kim

Sang Jin Cha

An EMI shielded semiconductor package is provided. The package includes a substrate and a chip disposed on the substrate. The chip is electrically connected to the substrate by a plurality of bonding wires. At least one shielding conductive block is formed on the substrate and electrically connected to the ground trace of the substrate. A sealant is formed on the substrate and covers the chip, bonding wires and the shielding conductive block. The sealant has a side surface to expose a surface of the shielding conductive block. A layer of conductive film is formed on the outer surface of the sealant and covers the exposed surface of the shielding conductive block thereby shielding the chip from electromagnetic interference.

EMI shielded semiconductor package

A semiconductor package structure and a method for manufacturing the same are disclosed. The semiconductor package structure includes a substrate, an interposer (such as a circuitry laminate), a metal layer formed on the interposer, a first chip and a second chip, wherein the interposer is disposed on the substrate and covers at least a portion of an opening of the substrate, thereby defining a space for receiving the first chip, and the second chip is disposed on the metal layer or the interposer. The metal layer is electrically connected to the substrate and grounded. The first chip is electrically connected to the substrate.

Semiconductor package structure and method for manufacturing the same

A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.

Process and lead frame for making leadless semiconductor packages

A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.

A singulation method comprising: (a) providing a molded product including semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and cutting streets between the units, each unit having a die pad and leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.

Growing community of inventors

Paju-si, South Korea

Hyeongno Kim