Samsung Electronics Co., Ltd.

Hyeong-Seob Kim

Tae-Gyeong Chung

Sang-Wook Park

Sa-Yoon Kang

In-Ku Kang

Min-Young Son

Ki-Kwon Jeong

Kwan-Jai Lee

Myung-Kee Chung

Provided is a semiconductor package apparatus having a redistribution layer. The apparatus includes at least one or more semiconductor chips, a packing part protecting the semiconductor chips, and a support part supporting the semiconductor chips. The apparatus also includes external terminals extending outside the packing part, redistribution layers installed between the semiconductor chips and the support part and including redistribution paths, first signal transmitting units, and second signal transmitting units. The first signal transmitting units transmitting electrical signals generated from the semiconductor chips to the redistribution paths of the redistribution layers, and the second signal transmitting units transmit the electrical signals from the redistribution paths to the external terminals. Therefore, a size and a thickness of the semiconductor package apparatus can be reduced, and processes can be simplified to improve productivity.

Semiconductor package apparatus having redistribution layer

A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.

Wafer level package, multi-package stack, and method of manufacturing the same

A semiconductor package having an ultra thin thickness and a method of manufacturing the same are provided. The ultra thin semiconductor package comprises a circuit board in which a through hole is formed. A semiconductor chip is located in the through hole and a connecting element electrically connects the circuit board and the semiconductor chip. An epoxy molding compound (EMC) covers the semiconductor chip and the connecting element and a supporter having a thermal expansion coefficient similar to the EMC is attached inside the through hole on a lower surface of the semiconductor chip. An external connecting terminal is attached to at least one side of the circuit board. Because of the inclusion of the supporter, warpage of the semiconductor package resulting from the curing of the EMC is prevented.

Semiconductor package having ultra-thin thickness and method of manufacturing the same

Wafer level package and multi-package stack

A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N&minus;1) chip selection pads, an insulation layer, (N&minus;1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof

A semiconductor chip is provided comprising a semiconductor substrate having determined circuit elements on it, a surface-smoothing layer deposited on the substrate, a bonding pad formed on the smoothing layer and connected electrically to the circuit elements, a passivation layer formed on the surface-smoothing layer, the passivation layer having a window for exposing a part of the bonding pad, and a second metal layer having a same height as the passivation layer and occupying peripheral parts of the window to form a reduced bonding windows for the bonding pad.

Growing community of inventors

Chungcheongnam-do, South Korea

Hyeong-Seob Kim