Vantis Corporation

Hyeon-Seag Kim

Sunil D Mehta

This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench-trench short circuiting. The improved electrical and mechanical properties of the shallow trench filling materials makes practical the manufacture of more reliable, smaller semiconductor devices.

Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress

Methods of manufacturing insulating materials and semiconductor devices incorporating films having high dielectric constants are disclosed, in which the high-dielectric constant material is deposited on a semiconductor surface that has been treated to prevent the formation of interfacial oxide between the semiconductor substrate and the high, dielectric constant material. The methods of this invention involve implantation of nitrogen ions through the sacrificial oxide layer, thereby forming a nitrided silicon substrate underneath the sacrificial oxide. The sacrificial oxide can then removed, and thereafter layers of high dielectric constant materials can be deposited on the nitrided silicon substrate without the formation of interfacial oxide. Manufacturing devices using the methods of this invention can result in the formation of an overall insulating film having a dielectric constant that more closely reflects the dielectric constant of the high-dielectric constant material. Therefore, the insulating films made using the methods of this invention can be made thinner than conventional insulating films, thus permitting the manufacture of semiconductor products having increasing device density and increasing efficiency, and decreasing manufacturing costs.

Gate insulator process for nanometer MOSFETS

This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench&mdash;trench short circuiting. The improved electrical and mechanical properties of the shallow trench filling materials makes practical the manufacture of more reliable, smaller semiconductor devices.

With the present invention, a filled isolation trench is fabricated as part of an integrated circuit on a semiconductor wafer using nitrogen implantation into at least one side wall of the isolation trench. An isolation trench is etched within a layer of semiconductor material. The isolation trench has at least one side wall comprised of the semiconductor material, and the isolation trench has a bottom wall. Nitrogen ions are implanted into the at least one side wall of the isolation trench. A layer of an insulator material is thermally grown from the at least one side wall and the bottom wall of the isolation trench. The isolation trench is then filled with the insulator material using a deposition process to form the filled isolation trench. With the present invention, the nitrogen ions implanted into the at least one side wall of the isolation trench reduce a radius of a bird's beak formed on the at least one side wall of the isolation trench. In addition, the nitrogen ions implanted into the at least one side wall of the isolation trench reduce mechanical stress on the at least one side wall of the isolation trench from the insulator material filling the isolation trench.

Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench

The present invention is a method for fabricating a plurality of oxide regions having a plurality of thicknesses on a semiconductor wafer. The present invention includes a step of depositing a first masking layer on the semiconductor wafer, and the first masking layer defines at least one first region for oxide growth of a first thickness. The present invention also includes a step of implanting oxygen ions into the at least one first region such that the first thickness of oxide on the at least one first region is relatively thicker. The first masking layer is then removed from the semiconductor wafer. The present invention further includes a step of depositing a second masking layer on the semiconductor wafer, and the second masking layer defines at least one second region for oxide growth of a second thickness. The present invention also includes a step of implanting nitrogen ions into the at least one second region such that the second thickness of oxide on the at least one second region is relatively thinner. The second masking layer is then removed from the semiconductor wafer. The present invention further includes the step of growing oxide on the at least one first region to have the first thickness and on the at least one second region to have the second thickness with a thermal process for the semiconductor wafer. During the thermal process, at least one third region of oxide may be grown to have a third thickness which is thinner than the oxide on the at least one first region and that is thicker than the oxide on the at least one second region since the at least one third region has not been exposed to oxygen ion implantation nor to nitrogen ion implantation.

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Sunnyvale, CA, United States of America

Hyeon-Seag Kim